公开(公告)号：US07868386B2

公开(公告)日：2011-01-11

申请号：US12058997

申请日：2008-03-31

Applicant: Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

Inventor： Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

IPC: H01L23/58 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

Abstract: A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

Abstract translation: 公开了一种具有改善的源极/漏极结的半导体器件和用于制造该器件的方法。 优选实施例包括具有覆盖在衬底上的栅极结构的MOS晶体管，形成在衬底中的与栅极结构对准的轻掺杂源极/漏极区域，形成在栅极结构的侧壁上并叠置在轻掺杂源极/漏极区域 形成在衬底中的更深的源极/漏极扩散与侧壁间隔物对准，并且在较深的源极/漏极扩散和衬底的边界处形成的源极/漏极掺杂剂的另外的凹穴注入。 在优选的方法中，使用角度离子植入物形成额外的袋状植入物，该角度离垂直方向在4度与45度之间。 另外的实施例包括在源极/漏极区域中形成的凹部和用于形成凹部的方法。

公开(公告)号：US07868361B2

公开(公告)日：2011-01-11

申请号：US11766425

申请日：2007-06-21

Applicant: Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong Song Liang

Inventor： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong Song Liang

IPC: H01L21/76

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

公开(公告)号：US07803674B2

公开(公告)日：2010-09-28

申请号：US12468131

申请日：2009-05-19

Applicant: Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

Inventor： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

IPC: H01L21/84

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/78636

Abstract: Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

Abstract translation: 提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。 在衬底上形成第一绝缘层。 在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。 在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。 在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。 第一电介质层形成在每个半导体岛的一部分上。 导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。 一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

公开(公告)号：US20080003734A1

公开(公告)日：2008-01-03

申请号：US11520377

申请日：2006-09-13

Applicant: Harry Chuang ,  Mong-Song Liang ,  Kong-Beng Thei ,  Jung-Hui Kao ,  Chung Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo

Inventor： Harry Chuang ,  Mong-Song Liang ,  Kong-Beng Thei ,  Jung-Hui Kao ,  Chung Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/7843

Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate comprising a first region and a second region, forming a first PMOS device in the first region wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration, forming a stress memorization layer over the first PMOS device, reducing the stress memorization layer in the first region, performing an annealing after the step of reducing the stress memorization layer in the first region, and removing the stress memorization layer. The same stress memorization layer is not reduced in a region having an NMOS device. The same stress memorization layer may not be reduced in a region including a second PMOS device.

Abstract translation: 一种形成半导体结构的方法包括提供包括第一区域和第二区域的半导体衬底，在第一区域中形成第一PMOS器件，其中第一PMOS器件的第一栅电极具有第一p型杂质浓度，形成 在第一PMOS器件上方的应力记忆层，减小第一区域中的应力存储层，在减少第一区域中的应力存储层的步骤之后进行退火，以及去除应力存储层。 在具有NMOS器件的区域中，相同的应力记忆层没有减小。 在包括第二PMOS器件的区域中，相同的应力记忆层可能不会减小。

公开(公告)号：US08174091B2

公开(公告)日：2012-05-08

申请号：US12503641

申请日：2009-07-15

Applicant: Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

Inventor： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC: H01L29/00

CPC classification number: H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

Abstract translation: 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

公开(公告)号：US08153498B2

公开(公告)日：2012-04-10

申请号：US12401876

申请日：2009-03-11

Applicant: Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

Inventor： Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

IPC: H01L21/8232

CPC classification number: H01L27/0629 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/66545 ,  Y10S438/926

Abstract: A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.

Abstract translation: 公开了一种用于制造在栅极替换处理中保护电阻结构的半导体器件的半导体器件和方法。 该方法包括提供半导体衬底; 在半导体衬底上形成包括虚拟栅极的至少一个栅极结构; 在半导体衬底上形成包括栅极的至少一个电阻结构; 暴露所述至少一个电阻结构的栅极的一部分; 在所述半导体衬底上形成蚀刻停止层，包括在所述栅极的暴露部分上方; 从所述至少一个门结构移除所述伪栅极以产生开口; 以及在所述至少一个栅极结构的开口中形成金属栅极。

公开(公告)号：US07768069B2

公开(公告)日：2010-08-03

申请号：US11334974

申请日：2006-01-18

Applicant: Chung-Long Cheng ,  Kong-Beng Thei

Inventor： Chung-Long Cheng ,  Kong-Beng Thei

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L29/785 ,  H01L21/32139 ,  H01L29/42384 ,  H01L29/66795

Abstract: A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket planarizing layer is formed as a planarizing layer, a photoresist layer formed thereupon is formed with enhanced resolution. As a result, the gate electrode is also formed with enhanced resolution. A resulting FIN-FET structure has the patterned planarizing layer formed in an inverted “U” shape upon the gate electrode.

Abstract translation: 用于形成FIN-FET器件的方法使用形成在覆盖的地形栅电极材料层上的覆盖平坦化层。 图案化覆盖层平坦化层并用作掩模层，用于图案化覆盖层形成的栅电极材料层以形成栅电极。 由于覆盖平坦化层形成为平坦化层，所以在其上形成的光致抗蚀剂层以更高的分辨率形成。 结果，栅电极也形成了增强的分辨率。 所得到的FIN-FET结构具有在栅电极上以倒U形形成的图案化平坦化层。

公开(公告)号：US20100087043A1

公开(公告)日：2010-04-08

申请号：US12330347

申请日：2008-12-08

Applicant: Chung Long CHENG ,  Kong-Beng THEI ,  Harry CHUANG

Inventor： Chung Long CHENG ,  Kong-Beng THEI ,  Harry CHUANG

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/105

Abstract: A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a substrate including a first region and a second region; forming at least one isolation region having a first aspect ratio in the first region and at least one isolation region having a second aspect ratio in the second region; performing a high aspect ratio deposition process to form a first layer over the first and second regions of the substrate; removing the first layer from the second region; and performing a high density plasma deposition process to form a second layer over the first and second regions of the substrate.

Abstract translation: 公开了一种制造具有改进性能的半导体器件的方法。 该方法包括提供包括第一区域和第二区域的衬底; 在所述第一区域中形成具有第一纵横比的至少一个隔离区域和在所述第二区域中具有第二纵横比的至少一个隔离区域; 执行高纵横比沉积工艺以在所述基板的所述第一和第二区域上形成第一层; 从第二区域去除第一层; 以及执行高密度等离子体沉积工艺以在所述衬底的所述第一和第二区域上形成第二层。

公开(公告)号：US07632729B2

公开(公告)日：2009-12-15

申请号：US11527616

申请日：2006-09-27

Applicant: Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

Inventor： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/7843

Abstract: A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.

Abstract translation: 公开了制造半导体器件的方法。 该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。 在NMOS和PMOS器件上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。 在NMOS和PMOS器件上进行第一次热处理。 去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

公开(公告)号：US20090218623A1

公开(公告)日：2009-09-03

申请号：US12468137

申请日：2009-05-19

Applicant: Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

Inventor： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/78636

Abstract: Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.