公开(公告)号：US20120286368A1

公开(公告)日：2012-11-15

申请号：US13558109

申请日：2012-07-25

申请人： Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

IPC分类号： H01L27/088

CPC分类号： H01L27/0207 ,  H01L27/11 ,  H01L27/1104

摘要： A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.

摘要翻译： 半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。 每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。 半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。

公开(公告)号：US08174091B2

公开(公告)日：2012-05-08

申请号：US12503641

申请日：2009-07-15

申请人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

发明人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

摘要翻译： 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

公开(公告)号：US20080315320A1

公开(公告)日：2008-12-25

申请号：US11766425

申请日：2007-06-21

申请人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong Song Liang

发明人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong Song Liang

IPC分类号： H01L29/76 ,  H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

公开(公告)号：US20080296691A1

公开(公告)日：2008-12-04

申请号：US11807654

申请日：2007-05-30

申请人： Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

IPC分类号： H01L29/76

CPC分类号： H01L27/0207 ,  H01L27/11 ,  H01L27/1104

摘要： A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.

摘要翻译： 半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。 每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。 半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。

公开(公告)号：US20080263492A1

公开(公告)日：2008-10-23

申请号：US11833119

申请日：2007-08-02

申请人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Sheng-Chen Chung ,  Chih-Tsung Yao ,  Jung-Hui Kao ,  Chung Long Cheng ,  Gary Shen ,  Gwan Sin Chang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Sheng-Chen Chung ,  Chih-Tsung Yao ,  Jung-Hui Kao ,  Chung Long Cheng ,  Gary Shen ,  Gwan Sin Chang

IPC分类号： G06F17/50

CPC分类号： H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.

摘要翻译： 提供了一种用于定义诸如finFET的3-D器件的布局的方法。 该方法包括确定期望的3-D设备所需的区域和使用具有等效面积的平面设备来设计电路。 对应于期望的3-D器件的平面器件用于布局电路设计，从而允许电路和布局设计者在更高级别工作，而不需要指定每个单独的鳍或3-D结构。 此后，平面设计可以通过用占据等同面积的3-D器件代替平面有源区域而被转换成3维设计。

公开(公告)号：US20080258228A1

公开(公告)日：2008-10-23

申请号：US11833128

申请日：2007-08-02

申请人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Jung-Hui Kao ,  Sheng-Chen Chung ,  Chung Long Cheng ,  Shun-Jang Liao

发明人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Jung-Hui Kao ,  Sheng-Chen Chung ,  Chung Long Cheng ,  Shun-Jang Liao

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via is connected to the contact.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的第一层间电介质（ILD）; 从第一ILD的顶表面延伸到第一ILD中的接触; 第一个ILD的第二个ILD; 在第二ILD上的底部金属间电介质（IMD）; 以及包括IMD中的金属线和第二ILD中的通孔的双镶嵌结构，其中所述通孔连接到所述触点。

公开(公告)号：US20080020533A1

公开(公告)日：2008-01-24

申请号：US11490012

申请日：2006-07-20

申请人： Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

发明人： Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

摘要翻译： 公开了一种具有改善的源极/漏极结的半导体器件和用于制造器件的方法。 优选实施例包括具有覆盖在衬底上的栅极结构的MOS晶体管，形成在衬底中的与栅极结构对准的轻掺杂源极/漏极区域，形成在栅极结构的侧壁上并叠置在轻掺杂源极/漏极区域 形成在衬底中的更深的源极/漏极扩散与侧壁间隔物对准，并且在较深的源极/漏极扩散和衬底的边界处形成的源极/漏极掺杂剂的另外的凹穴注入。 在优选的方法中，使用角度离子植入物形成额外的袋状植入物，该角度离垂直方向在4度和45度之间。 另外的实施例包括在源极/漏极区域中形成的凹部和用于形成凹部的方法。

公开(公告)号：US08367515B2

公开(公告)日：2013-02-05

申请号：US12330347

申请日：2008-12-08

申请人： Chung Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

发明人： Chung Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/105

摘要： A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a substrate including a first region and a second region; forming at least one isolation region having a first aspect ratio in the first region and at least one isolation region having a second aspect ratio in the second region; performing a high aspect ratio deposition process to form a first layer over the first and second regions of the substrate; removing the first layer from the second region; and performing a high density plasma deposition process to form a second layer over the first and second regions of the substrate.

摘要翻译： 公开了一种制造具有改进性能的半导体器件的方法。 该方法包括提供包括第一区域和第二区域的衬底; 在所述第一区域中形成具有第一纵横比的至少一个隔离区域和在所述第二区域中具有第二纵横比的至少一个隔离区域; 执行高纵横比沉积工艺以在所述基板的所述第一和第二区域上形成第一层; 从第二区域去除第一层; 以及执行高密度等离子体沉积工艺以在所述衬底的所述第一和第二区域上形成第二层。

公开(公告)号：US08286114B2

公开(公告)日：2012-10-09

申请号：US11833119

申请日：2007-08-02

申请人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Sheng-Chen Chung ,  Chih-Tsung Yao ,  Jung-Hui Kao ,  Chung Long Cheng ,  Gary Shen ,  Gwan Sin Chang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Sheng-Chen Chung ,  Chih-Tsung Yao ,  Jung-Hui Kao ,  Chung Long Cheng ,  Gary Shen ,  Gwan Sin Chang

IPC分类号： G06F17/50

CPC分类号： H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.

摘要翻译： 提供了一种用于定义诸如finFET的3-D器件的布局的方法。 该方法包括确定期望的3-D设备所需的区域和使用具有等效面积的平面设备来设计电路。 对应于期望的3-D器件的平面器件用于布局电路设计，从而允许电路和布局设计者在更高级别工作，而不需要指定每个单独的鳍或3-D结构。 此后，平面设计可以通过用占据等同面积的3-D器件代替平面有源区域而被转换成3维设计。

公开(公告)号：US20110260251A1

公开(公告)日：2011-10-27

申请号：US13178755

申请日：2011-07-08

申请人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

发明人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC分类号： H01L27/12

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。