公开(公告)号：US08669597B2

公开(公告)日：2014-03-11

申请号：US12116200

申请日：2008-05-06

申请人： Shenqing Fang ,  Connie Wang ,  Wen Yu ,  Fei Wang

发明人： Shenqing Fang ,  Connie Wang ,  Wen Yu ,  Fei Wang

IPC分类号： H01L29/66 ,  H01L21/4763

CPC分类号： H01L23/528 ,  H01L21/76807 ,  H01L21/76813 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.

摘要翻译： 在一个实施例中，集成电路存储器件包括具有多个位线的衬底。 第一和第二层间电介质层依次设置在基板上。 多个源极线和交错位线触点中的每一个延伸穿过第一层间电介质层。 多个源极线路通孔和多个交错位线通孔中的每一条通过第二级间介电层延伸到多条源极线路和多条交错位线触点中的每一个。 通过第一组制造工艺一起形成延伸穿过第一层间电介质层的源极线和交错位线触点。 延伸穿过第二层间电介质层的源极线通孔和交错位线触点也通过第二组制造工艺一起形成。

公开(公告)号：US07696092B2

公开(公告)日：2010-04-13

申请号：US09994395

申请日：2001-11-26

申请人： Sergey D. Lopatin ,  Paul R. Besser ,  Pin-Chin Connie Wang

发明人： Sergey D. Lopatin ,  Paul R. Besser ,  Pin-Chin Connie Wang

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating an integrated circuit includes forming a barrier layer along lateral side walls and a bottom of a via aperture and providing a ternary copper alloy via material in the via aperture to form a via. The via aperture is configured to receive the ternary copper alloy via material and electrically connect a first conductive layer and a second conductive layer. The ternary copper alloy via material helps the via to have a lower resistance and an increased grain size with staffed grain boundaries.

摘要翻译： 一种制造集成电路的方法包括沿着横向侧壁和通孔孔的底部形成阻挡层，并且在通孔中通过材料提供三元铜合金以形成通孔。 通孔被配置成通过材料接收三元铜合金并电连接第一导电层和第二导电层。 三元铜合金通孔材料有助于通孔具有较低的电阻和增加的晶粒尺寸与人工晶界。

公开(公告)号：US20090278173A1

公开(公告)日：2009-11-12

申请号：US12116200

申请日：2008-05-06

申请人： Shenqing FANG ,  Connie WANG ,  Wen YU ,  Fei WANG

发明人： Shenqing FANG ,  Connie WANG ,  Wen YU ,  Fei WANG

IPC分类号： H01L29/66 ,  H01L21/4763

CPC分类号： H01L23/528 ,  H01L21/76807 ,  H01L21/76813 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.

摘要翻译： 在一个实施例中，集成电路存储器件包括具有多个位线的衬底。 第一和第二层间电介质层依次设置在基板上。 多个源极线和交错位线触点中的每一个延伸穿过第一层间电介质层。 多个源极线路通孔和多个交错位线通孔中的每一条通过第二级间介电层延伸到多条源极线路和多条交错位线触点中的每一个。 通过第一组制造工艺一起形成延伸穿过第一层间电介质层的源极线和交错位线触点。 延伸穿过第二层间电介质层的源极线通孔和交错位线触点也通过第二组制造工艺一起形成。

公开(公告)号：US20050085073A1

公开(公告)日：2005-04-21

申请号：US10687186

申请日：2003-10-16

申请人： Sergey Lopatin ,  Paul Besser ,  Alline Myers ,  Jeremias Romero ,  Minh Tran ,  Lu You ,  Connie Wang

发明人： Sergey Lopatin ,  Paul Besser ,  Alline Myers ,  Jeremias Romero ,  Minh Tran ,  Lu You ,  Connie Wang

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76846 ,  H01L21/76877

摘要： An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.

摘要翻译： 示例性实施例涉及在集成电路制造工艺中使用粘附前体的方法。 该方法包括在介电材料上提供材料的气体并在粘附前体层上提供铜层。 粘附前体层由气体形成，电介质材料包括孔。

公开(公告)号：US06617176B1

公开(公告)日：2003-09-09

申请号：US10152861

申请日：2002-05-21

申请人： John E. Sanchez, Jr. ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo ,  Paul R. Besser

发明人： John E. Sanchez, Jr. ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo ,  Paul R. Besser

IPC分类号： H01L2166

CPC分类号： H01L22/24 ,  G01N1/32 ,  H01L22/34

摘要： A method (M) of determining the effectiveness of a deposited thin conformal barrier layer (30) by forming a test specimen and measuring the copper (Cu) penetration from a metallization layer (40) through the barrier layer (30) (e.g., refractory metals, their nitrides, their carbides, or their other compounds), through a thin insulating dielectric layer (20) (e.g., SiO2), and into a semiconductor (10) substrate (e.g., Si), wherein the interaction between the migrating metal ions and the semiconductor ions are detected/monitored, and wherein the detection/monitoring comprises (1) stripping at least a portion of the insulating dielectric layer (20) and the barrier layer (30) and (2) examining the semiconductor substrate (10) surface of the test specimen, thereby improving interconnect reliability, enhancing electromigration resistance, improving corrosion resistance, reducing copper diffusion, and a test specimen device thereby formed.

摘要翻译： 通过形成测试样品并测量从金属化层（40）穿过阻挡层（30）（例如耐火材料）的铜（Cu）渗透性来确定沉积的薄共形阻挡层（30）的有效性的方法（M） 金属，其氮化物，它们的碳化物或其它化合物）通过薄的绝缘介电层（20）（例如SiO 2）和半导体（10）衬底（例如Si）中，其中迁移金属 离子和半导体离子被检测/监测，并且其中检测/监测包括（1）剥离绝缘介电层（20）和阻挡层（30）的至少一部分和（2）检查半导体衬底（10） ）表面，从而提高互连可靠性，提高耐迁移性，提高耐腐蚀性，减少铜扩散，从而形成试样装置。

公开(公告)号：US06590288B1

公开(公告)日：2003-07-08

申请号：US09874549

申请日：2001-06-04

申请人： Christy Mei-Chu Woo ,  Pin-Chin Connie Wang ,  Amit P. Marathe

发明人： Christy Mei-Chu Woo ,  Pin-Chin Connie Wang ,  Amit P. Marathe

IPC分类号： H01L2348

CPC分类号： H01L21/76846 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/76873 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first conductor core is connected to the semiconductor device. A low dielectric constant dielectric layer is formed over the semiconductor substrate and has an opening formed therein. A first barrier layer is deposited over the first conductor core. A second barrier layer is deposited to line the low dielectric constant dielectric layer and the first barrier layer. A third barrier layer is deposited to line the second barrier layer. A second conductor core is deposited to fill the opening over the third barrier layer.

摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路及其制造方法。 第一导体芯连接到半导体器件。 在半导体衬底上形成低介电常数介质层，并且其中形成有开口。 第一阻挡层沉积在第一导体芯上。 沉积第二阻挡层以对低介电常数介电层和第一阻挡层进行排列。 沉积第三阻挡层以使第二阻挡层成线。 沉积第二导体芯以填充第三阻挡层上的开口。

公开(公告)号：US06589408B1

公开(公告)日：2003-07-08

申请号：US10107778

申请日：2002-03-27

申请人： Pin-Chin Connie Wang ,  Paul R. Besser ,  Sergey D. Lopatin ,  Minh Q. Tran

发明人： Pin-Chin Connie Wang ,  Paul R. Besser ,  Sergey D. Lopatin ,  Minh Q. Tran

IPC分类号： C23C1435

CPC分类号： C23C14/3414 ,  C23C14/3407

摘要： A non-planar target can be configured for use in a plasma vapor deposition (PVD) process in which ions bombard the non-planar target and cause alloy atoms present in the non-planar target to be knocked loose and form an alloy film layer. The target includes a top planar section having a first alloy concentration and a side annular section having a second alloy concentration. The side annular section has ends coupled to ends of the top planar section. The first alloy concentration and the second alloy concentration are different.

摘要翻译： 非平面靶可以被配置用于等离子体气相沉积（PVD）工艺，其中离子轰击非平面靶，并使存在于非平面靶中的合金原子被敲击松动并形成合金膜层。 目标包括具有第一合金浓度的顶部平面部分和具有第二合金浓度的侧部环形部分。 侧面环形部分具有端部连接到顶部平面部分的端部。 第一合金浓度和第二合金浓度不同。

公开(公告)号：US06548395B1

公开(公告)日：2003-04-15

申请号：US09713313

申请日：2000-11-16

申请人： Christy Mei-Chu Woo ,  Pin-Chin Connie Wang

发明人： Christy Mei-Chu Woo ,  Pin-Chin Connie Wang

IPC分类号： H01L214763

CPC分类号： H01L21/76877

摘要： Cu or a Cu alloy is deposited to partially fill openings in a dielectric layer and then annealed. Incomplete filling leaves room in the openings to accommodate a volume change associated with grain growth and, hence, prevents the generation of voids. The openings are then completely filled, annealed a second time and then planarized, as by CMP. Embodiments include partially filling about 70% to about 90% of the volume of the trenches and then annealing before completely filling the trenches.

摘要翻译： 沉积Cu或Cu合金以部分地填充介电层中的开口，然后退火。 不完全填充在开口中留下空间以适应与晶粒生长相关的体积变化，并因此防止空隙的产生。 然后将开口完全填充，第二次退火然后平坦化，如CMP。 实施例包括部分填充约70％至约90％的沟槽体积，然后在完全填充沟槽之前进行退火。

公开(公告)号：US06531780B1

公开(公告)日：2003-03-11

申请号：US09894289

申请日：2001-06-27

申请人： Christy Mei-Chu Woo ,  Pin-Chin Connie Wang ,  Amit P. Marathe

发明人： Christy Mei-Chu Woo ,  Pin-Chin Connie Wang ,  Amit P. Marathe

IPC分类号： H01L2348

CPC分类号： H01L21/76844 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first channel dielectric layer over the semiconductor has a first opening lined by a first barrier layer and filled by a first conductor core. A via dielectric layer having a via opening which is open to the first conductor core is formed over the first channel dielectric layer. A second channel dielectric layer with a second opening which is open to the via is formed over the via dielectric layer. A second conductor core fills the via and second channel openings. A second barrier layer lining the via and second channel openings under the second conductor core forms a barrier between the second conductor core and the via and second channel dielectric layers, but does not form a barrier between the first and the second conductor cores.

摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路及其制造方法。 半导体上的第一通道电介质层具有由第一阻挡层衬里并由第一导体芯填充的第一开口。 在第一沟道电介质层上形成具有通向第一导体芯开口的通路开口的通孔电介质层。 在通孔电介质层上形成具有对通孔开口的第二开口的第二通道电介质层。 第二导体芯填充通孔和第二通道开口。 衬在第二导体芯下方的通孔和第二通道开口的第二阻挡层在第二导体芯与通孔和第二通道介电层之间形成阻挡层，但不形成第一和第二导体芯之间的阻挡层。

公开(公告)号：US06518185B1

公开(公告)日：2003-02-11

申请号：US10127521

申请日：2002-04-22

申请人： Pin-Chin Connie Wang ,  Fei Wang ,  Kashmir Sahota ,  Steven Avanzino ,  Amit Marathe ,  Matthew Buynoski ,  Ercan Adem ,  Christy Woo

发明人： Pin-Chin Connie Wang ,  Fei Wang ,  Kashmir Sahota ,  Steven Avanzino ,  Amit Marathe ,  Matthew Buynoski ,  Ercan Adem ,  Christy Woo

IPC分类号： H01L2144

CPC分类号： H01L21/76877

摘要： In the present method of fabricating a semiconductor device, openings of different configurations (for example, different aspect ratios) are provided in a dielectric layer. Substantially undoped copper is deposited over the dielectric layer, filling the openings and extending above the dielectric layer, the different configurations of the openings providing an upper surface of the substantially undoped copper that is generally non-planar. A portion of the substantially undoped copper is removed to provide a substantially planar upper surface thereof, and a layer of doped copper is deposited on the upper surface of the substantially undoped copper. An anneal step is undertaken to difffuse the doping element into the copper in the openings.

摘要翻译： 在本发明的半导体装置的制造方法中，在介质层中设置不同结构（例如不同的纵横比）的开口。 基本上未掺杂的铜沉积在电介质层上，填充开口并在电介质层上方延伸，开口的不同构型提供通常为非平面的基本未掺杂的铜的上表面。 去除基本上未掺杂的铜的一部分以提供其基本平坦的上表面，并且在基本未掺杂的铜的上表面上沉积掺杂的铜层。 进行退火步骤以将掺杂元素扩散到开口中的铜中。