公开(公告)号：US20080148024A1

公开(公告)日：2008-06-19

申请号：US11610871

申请日：2006-12-14

Applicant: Gilbert M. Wolrich ,  William Hasenplaugh ,  Wajdi Feghali ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

Inventor： Gilbert M. Wolrich ,  William Hasenplaugh ,  Wajdi Feghali ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

IPC: G06F9/302

CPC classification number: G06F9/30014 ,  G06F21/72

Abstract: The present disclosure provides a method for instruction processing. The method may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit. The method may further include loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand. The method may also include performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register. The method may further include loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand. The method may additionally include generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract translation: 本公开提供了一种用于指令处理的方法。 该方法可以包括从第一寄存器，第二操作数，第二寄存器和进位输入位添加第一操作数，以产生和和执行位。 该方法还可以包括将和加载到第三寄存器中，并且将进位位加载到第三寄存器的最高有效位位置以产生第三操作数。 该方法还可以包括经由移位器单元在第三操作数上执行单位移位以产生移位的操作数，并将移位的操作数加载到第四寄存器中。 该方法还可以包括将最小有效位加载到第四寄存器的最高有效位位置以产生第四操作数。 该方法可以另外包括经由第四操作数生成第一和第二操作数的最大公约数（GCD），并且至少部分地基于GCD生成公钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20080013715A1

公开(公告)日：2008-01-17

申请号：US11323993

申请日：2005-12-30

Applicant: Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

Inventor： Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

IPC: H04L9/28

CPC classification number: G06F7/52 ,  G06F9/3001 ,  G06F9/3881 ,  G06F9/3885 ,  G06F21/72

Abstract: In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.

Abstract translation: 通常，在一个方面，本公开描述了包括多个可编程处理单元，专用硬件乘法器和连接多个处理单元和乘法器的至少一个总线的系统。

公开(公告)号：US20070192547A1

公开(公告)日：2007-08-16

申请号：US11354404

申请日：2006-02-14

Applicant: Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal

Inventor： Wajdi Feghali ,  William Hasenplaugh ,  Gilbert Wolrich ,  Daniel Cutter ,  Vinodh Gopal

IPC: G06F13/00 ,  G06F12/00

CPC classification number: G06F9/30145 ,  G06F7/5324 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/383 ,  G06F21/602 ,  G06F21/72

Abstract: In general, in one aspect, the disclosure describes a processing unit that includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control store of program instructions, the control logic to process instructions including an instruction to transfer data from the input buffer to the memory and an instruction to cause the arithmetic logic unit to perform an operation on operands provided by at least one of the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.

Abstract translation: 通常，在一个方面，本发明描述了一种处理单元，其包括用于存储由处理单元接收的数据的输入缓冲器，存储器，耦合到输入缓冲器和存储器的算术逻辑单元，输出缓冲器; 以及具有访问程序指令的控制存储的控制逻辑，所述控制逻辑用于处理包括将数据从所述输入缓冲器传送到所述存储器的指令的指令，以及使所述算术逻辑单元对由所述输入缓冲器提供的操作数执行操作的指令 至少一个存储器和输入缓冲器，将操作结果输出到至少一个存储器和输出缓冲器的指令。

公开(公告)号：US06427196B1

公开(公告)日：2002-07-30

申请号：US09387110

申请日：1999-08-31

Applicant: Matthew J. Adiletta ,  William Wheeler ,  James Redfield ,  Daniel Cutter ,  Gilbert Wolrich

Inventor： Matthew J. Adiletta ,  William Wheeler ,  James Redfield ,  Daniel Cutter ,  Gilbert Wolrich

IPC: G06F1300

CPC classification number: G06F13/1642

Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of micro control functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Abstract translation: 用于随机存取存储器的控制器包括保存来自多个微控制功能单元的存储器引用的地址和命令队列。 地址和命令队列包括存储读取存储器引用的读取队列。 控制器还包括第一读/写队列，其保存来自核心处理器的存储器引用和控制逻辑，所述控制逻辑包括检测每个队列的完整性的仲裁器以及尚未完成的存储器引用的完成状态以从以下之一中选择存储器引用 排队。

公开(公告)号：US06324624B1

公开(公告)日：2001-11-27

申请号：US09473798

申请日：1999-12-28

Applicant: Gilbert Wolrich ,  Daniel Cutter ,  William Wheeler ,  Matthew J. Adiletta ,  Debra Bernstein

Inventor： Gilbert Wolrich ,  Daniel Cutter ,  William Wheeler ,  Matthew J. Adiletta ,  Debra Bernstein

IPC: G06F1318

CPC classification number: G06F9/52

Abstract: Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if (1) the read lock memory reference request is requesting access to an unlocked memory location and (2) the read lock miss queue contains at least one read lock memory reference request.

Abstract translation: 管理对随机存取存储器的存储器访问包括获取读锁定存储器引用请求并将读锁定存储器引用请求放置在读锁定未命中队列的末尾，如果（1）读锁定存储器引用请求正在请求访问解锁的存储器位置 和（2）读取锁定未命中队列至少包含一个读取锁定存储器引用请求。