-
公开(公告)号：US11588487B1
公开(公告)日：2023-02-21
申请号：US17488338
申请日：2021-09-29
Applicant: Faraday Technology Corp.
Inventor： Prateek Kumar Goyal , Chienlung Kung
Abstract: An eye opening monitor device and an operation method thereof are provided. The eye opening monitor device includes a phase interpolator, a first sampling circuit, a second sampling circuit, and a clock centering circuit. The first sampling circuit samples a data signal according to a data clock to generate first sampled data. The second sampling circuit samples the data signal according to a phase interpolation clock to generate second sampled data. The phase interpolator changes a phase of the phase interpolation clock according to a phase interpolation code. The clock centering circuit counts multiple comparison results of the first sampled data and the second sampled data in multiple clock cycles to obtain an error count value for any one of different phase interpolation codes. The clock centering circuit determines the phase interpolation code provided to the phase interpolator based on the error count values corresponding to different phase interpolation codes.
-
公开(公告)号：US11430783B2
公开(公告)日：2022-08-30
申请号：US16745349
申请日：2020-01-17
Applicant: Faraday Technology Corp.
Inventor： Chia-Ku Tsai , Tsung-Hsiao Lin
IPC: H01L27/02 , H01L29/861 , H01L27/092
Abstract: The electrostatic discharge (ESD) protection apparatus includes a first well, a second well, a first doping region, and a second doping region. The first well is disposed in a substrate having a first conductivity type, wherein the first well has a second conductivity type and the substrate is electrically connected to a first pad. The second well is disposed in the first well, wherein the second well has the first conductivity type. The first doping region is disposed in the second well, wherein the first doping region has the second conductivity type, and the first doping region is electrically connected to a second pad. The second doping region is disposed in the second well, wherein the second doping region has the first conductivity type.
-
23.发明申请公开(公告)号：US20220209818A1
公开(公告)日：2022-06-30
申请号：US17191655
申请日：2021-03-03
Applicant: Faraday Technology Corp.
Inventor： Chia Jung Chan , Wei-Cyuan Wu
IPC: H04B3/23
Abstract: An echo cancellation device and an echo cancellation method thereof applied in a communication device are provided. The echo cancellation device includes an echo canceller and a combine circuit. The echo canceller obtains a plurality of delayed signals from a local signal of the communication device, and the delayed signals are divided into a plurality of delayed signal groups. The echo canceller selectively ignores at least one of the delayed signal groups, and the echo canceller generates an echo cancellation signal with the others of the delayed signal groups. The combine circuit is coupled to an interface circuit of the communication device to receive a received signal. The combine circuit cancels an echo component of the received signal with the echo cancellation signal to generate a cancelled signal.
-
公开(公告)号：US11290309B2
公开(公告)日：2022-03-29
申请号：US17129799
申请日：2020-12-21
Applicant: Faraday Technology Corp.
Inventor： Shih-Yi Shih
IPC: H04L27/14 , H04L27/12 , H03M13/25 , H04L43/50 , H04L43/0817
Abstract: The present invention discloses a Trellis-Coded-Modulation (TCM) decoder applied in a receiver, wherein the TCM decoder includes a branch metric unit, a path metric unit, a trace-back length selection circuit and a survival path management circuit. In operations of the TCM decoder, the branch metric unit is configured to receive multiple input codes to generate multiple sets of branch information. The path metric unit is configured to calculate multiple survival paths according to the multiple sets of branch information. The trace-back length selection circuit is configured to select a trace-back length, wherein the trace-back length is determined according to a signal quality of the receiver. The survival path management circuit is configured to return the multiple survival paths for the trace-back length in order to generate an output code.
-
25.发明授权公开(公告)号：US11245408B2
公开(公告)日：2022-02-08
申请号：US17151673
申请日：2021-01-19
Applicant: FARADAY TECHNOLOGY CORPORATION , Faraday Technology Corp.
Inventor： Feng Xu , Chih-Yuan Hung , Meng Zhao
Abstract: A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.
-
Patent Agency Ranking
公开(公告)号：US10756674B2
公开(公告)日：2020-08-25
申请号：US16248795
申请日：2019-01-16
Applicant: Faraday Technology Corp.
Inventor： Hsu-Ming Tsai , Ta-Wei Wang
Abstract: An amplifier including a first routing circuit, an input stage circuit, an output stage circuit, a second routing circuit, and a bias voltage generating circuit is provided. The bias voltage generating circuit generates a first bias voltage and a second bias voltage for respectively supplying a first tail current source and a second tail current source of the input stage circuit. During a first period, the first bias voltage is related to the voltage at a first input terminal of the amplifier, and the second bias voltage is related to the voltage at a second input terminal of the amplifier. During a second period, the first bias voltage is related to the voltage at the second input terminal of the amplifier, and the second bias voltage is related to the voltage at the first input terminal of the amplifier.
-
公开(公告)号：US20200162025A1
公开(公告)日：2020-05-21
申请号：US16248795
申请日：2019-01-16
Applicant: Faraday Technology Corp.
Inventor： Hsu-Ming Tsai , Ta-Wei Wang
Abstract: An amplifier including a first routing circuit, an input stage circuit, an output stage circuit, a second routing circuit, and a bias voltage generating circuit is provided. The bias voltage generating circuit generates a first bias voltage and a second bias voltage for respectively supplying a first tail current source and a second tail current source of the input stage circuit. During a first period, the first bias voltage is related to the voltage at a first input terminal of the amplifier, and the second bias voltage is related to the voltage at a second input terminal of the amplifier. During a second period, the first bias voltage is related to the voltage at the second input terminal of the amplifier, and the second bias voltage is related to the voltage at the first input terminal of the amplifier.
-
公开(公告)号：US20190310676A1
公开(公告)日：2019-10-10
申请号：US16029648
申请日：2018-07-09
Applicant: Faraday Technology Corp.
Inventor： Jin-Sheng Chen
IPC: G05F3/26
Abstract: In a voltage generating circuit, a bandgap voltage generator has a first operational amplifier to receive a first voltage and a second voltage, and generate a bias voltage by comparing the first voltage and the second voltage, wherein the bandgap voltage generator generates a bandgap current according to the bias voltage and generates an output voltage according to the bandgap current. In a start-up circuit, a comparison circuit compares the first voltage or the second voltage with a reference voltage to generate a first comparison result, and generates a first current according to the first comparison result. A voltage regulator generates a second current according to the first current, and compares the second current with a reference current to generate a second comparison result, and adjusts a voltage value of the bias voltage according to the second comparison result.
-
公开(公告)号：US10326429B1
公开(公告)日：2019-06-18
申请号：US16053814
申请日：2018-08-03
Applicant: Faraday Technology Corp.
Inventor： Ming-Chi Lin
Abstract: A receiver and a common-mode voltage calibration method thereof are provided. The receiver includes sensing circuits, a phase comparator, and a self-calibration circuit. The phase comparator compares phase relationships of the latch results at the output terminals of the sensing circuits during a testing period to produce a phase comparison result. During the testing period, the self-calibration circuit provides the same differential signal to the input terminals of these sensing circuits, and sets common-mode levels at the input terminals of these sensing circuits to be different from one another. The self-calibration circuit determines a calibrated common-mode level based on the phase comparison result. The self-calibration circuit sets the common-mode levels at the input terminals of these sensing circuits to be equal to the calibrated common-mode level during a normal operation period.
-
公开(公告)号：US20180090110A1
公开(公告)日：2018-03-29
申请号：US15350117
申请日：2016-11-14
Applicant: Faraday Technology Corp.
Inventor： Cheng-Yen Huang , Chun-Yuan Lai
Abstract: An apparatus and a method for video frame rotation are provided. The apparatus includes a synchronous dynamic random access memory (SDRAM) and a video rotation circuit. The video rotation circuit is coupled to the SDRAM. The video rotation circuit sequentially writes a plurality of pixels of a video frame into the SDRAM in a row-by-row scanning manner. The video rotation circuit divides a plurality of columns of the video frame into a plurality of column sets, so as to divide each of the rows of the video frame into a plurality of sub-rows. The video rotation circuit performs an internal column-set scanning for each of the column sets in a column-set-by-column-set manner, so as to discretely read the sub-rows from the SDRAM.
-
-
-
-
-
-
-
-
-
Search Results
92
records
(took 0.024 seconds)
