摘要:
An apparatus and method are provided for performing register renaming, whereby architectural registers from a set of architectural registers are mapped to physical registers from a set of physical registers. Available register identifying circuitry is provided which is responsive to a current state of the apparatus to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration storage stores configuration data whose value is modified during operation of the processing circuitry, such that when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The available register identifying circuitry is arranged to reference the configuration storage, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers. This enables the performance benefits from performing register renaming to be improved, without the need to increase the number of physical registers within the physical register set.
摘要:
An apparatus for processing data includes diagnostic mechanisms for providing watch point and breakpoint functionality. Semaphores are associated with the watch points and are provided with hardware support within the diagnostic circuitry serving to monitor whether or not accesses to watch point data is being made in accordance with the permissions set up and noted in the semaphore data.
摘要:
A data processing apparatus and method are provided for handling execution of instructions within a data processing apparatus having a plurality of processing units. Each processing unit is operable to execute a sequence of instructions so as to perform associated operations, and at least a subset of the processing units form a cluster. Instruction forwarding logic is provided which for at least one instruction executed by at least one of the processing units in the cluster causes that instruction to be executed by each of the other processing units in the cluster, for example by causing that instruction to be inserted into the sequences of instructions executed by each of the other processing units in the cluster. Such a mechanism provides a particularly efficient technique to cause each of the processing units in the cluster to perform an identical operation which can be useful in a variety of situations, for example in an SMP system where coherency of data is required and accordingly maintenance operations need to be performed periodically within each processing unit to ensure such coherency.
摘要:
A data processing system 2 utilizes a register renaming mechanism 10, 26 to rename architectural register specifiers to physical register specifiers to facilitate out-of-order processing. The register renaming mechanism 10, 26 includes a renaming recovery unit 26 which enables recovery from incorrectly executed speculative instructions by restoring the register mapping to the state prior to those incorrect instructions with the physical registers restored to containing the data values which were current at the time prior to that incorrect instruction. In the case of load instructions, these are treated as speculative but the data value returned in response to the load instruction and stored within a physical register is released for use as soon as it is returned and prior to a determination result being available as to whether or not that data value is corrupt. Corruption checking an take the form of ECC checking, parity checking and the like, and when a late error signal is generated then this indicates whether or not the data value has been properly released for use. If corruption is detected, then the renaming recovery unit 26 is used to recover the state of the system 2 in a precise way to that preceding the failing load instruction.
摘要:
The present application discloses register renaming circuitry for mapping registers from an architectural set of registers to registers within a physical set of registers, said architectural set of registers being registers specified by instructions within an instruction set and said physical set of registers being registers within a processor for processing instructions of said instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way, said register renaming circuitry comprising: a first data store for storing a future renaming table, said future renaming table comprising renaming values for mapping registers from said architectural set of registers to registers in said physical set of registers for instructions that are to be executed or are currently being executed by said processor; a second data store for storing a recovery renaming table, said recovery renaming table comprising a most recently committed mapping of said processor; wherein said register renaming circuitry is responsive to detection of a predetermined condition to mark said physical registers not mapped in said recovery renaming table as available for renaming.
摘要:
A data processing apparatus and method are provided for handling execution of instructions within a data processing apparatus having a plurality of processing units. Each processing unit is operable to execute a sequence of instructions so as to perform associated operations, and at least a subset of the processing units form a cluster. Instruction forwarding logic is provided which for at least one instruction executed by at least one of the processing units in the cluster causes that instruction to be executed by each of the other processing units in the cluster, for example by causing that instruction to be inserted into the sequences of instructions executed by each of the other processing units in the cluster. Such a mechanism provides a particularly efficient technique to cause each of the processing units in the cluster to perform an identical operation which can be useful in a variety of situations, for example in an SMP system where coherency of data is required and accordingly maintenance operations need to be performed periodically within each processing unit to ensure such coherency.
摘要:
A data processing system 2 utilises a register renaming mechanism 10, 26 to rename architectural register specifiers to physical register specifiers to facilitate out-of-order processing. The register renaming mechanism 10, 26 includes a renaming recovery unit 26 which enables recovery from incorrectly executed speculative instructions by restoring the register mapping to the state prior to those incorrect instructions with the physical registers restored to containing the data values which were current at the time prior to that incorrect instruction. In the case of load instructions, these are treated as speculative but the data value returned in response to the load instruction and stored within a physical register is released for use as soon as it is returned and prior to a determination result being available as to whether or not that data value is corrupt. Corruption checking an take the form of ECC checking, parity checking and the like, and when a late error signal is generated then this indicates whether or not the data value has been properly released for use. If corruption is detected, then the renaming recovery unit 26 is used to recover the state of the system 2 in a precise way to that preceding the failing load instruction.