公开(公告)号：US20220413961A1

公开(公告)日：2022-12-29

申请号：US17823131

申请日：2022-08-30

Applicant: Graphcore Limited

Inventor： Stephen FELIX ,  Daniel WILKINSON ,  Graham Bernard CUNNINGHAM

IPC: G06F11/10 ,  H03K19/21 ,  G06F11/07

Abstract: Signature generation circuitry is configured to update a signature in response to each of a plurality of writes to memory. The signature is updated by performing bitwise operations between current bit values of the signature and at least some of the bits written to memory in response a write. The bitwise operation are order-independent such that the resulting signature is the same irrespective of the order in which the writes are used to update the signature. The signatures are formed in an order-independent manner such that, if no errors have occurred in generating the data to be written to be memory, the signatures will match. In this way, a compact signature is developed that is suitable export from the data processing device for checking against a corresponding data processing device of a machine running a duplicate application.

公开(公告)号：US20220382707A1

公开(公告)日：2022-12-01

申请号：US17818855

申请日：2022-08-10

Applicant: Graphcore Limited

Inventor： Simon KNOWLES

IPC: G06F15/173 ,  G06N20/00 ,  G06K9/62

Abstract: A computer is provided, including a plurality of processing nodes arranged two-dimensional arrays in respective front and rear layers. Each processing node has a set of activatable links. When activated, transmission of data items between the nodes connected via the activated link is enabled. When not activated, transmission of data items between said nodes is prevented. The set of activatable links includes a respective link which connects the processing node to each adjacent node in the array, and to a facing processing node in the other layer. An allocation engine is configured to receive an allocation instruction and connected to the processing nodes to selectively activate the links in a configuration in which: (i) links between adjacent nodes are activated; (ii) links between facing nodes are only activated for edge processing nodes; and (iii) links between processing nodes outside the group and adjacent processing nodes in the group are deactivated.

公开(公告)号：US11507386B2

公开(公告)日：2022-11-22

申请号：US16527562

申请日：2019-07-31

Applicant: Graphcore Limited

Inventor： Daniel John Pelham Wilkinson

IPC: G06F9/44 ,  G06F9/4401

Abstract: A processing system comprises a first subsystem comprising at least one host processor and one or more storage units, and a second subsystem comprising at least one second processor. Each second processor comprises a plurality of tiles. Each tile comprises a processing unit and memory. At least one storage unit stores bootloader code for each of first and second subsets of the plurality of tiles of at least one second processor. The first subsystem writes bootloader code to each of the first subset of tiles of the at least one second processor. At least one of the first subset of tiles requests at least one of the storage units to return the bootloader code to the second subset of the plurality of tiles. Each tile to which the bootloader code is written retrieves boot code from the storage unit and then runs said boot code.

公开(公告)号：US11462293B2

公开(公告)日：2022-10-04

申请号：US17443061

申请日：2021-07-20

Applicant: Graphcore Limited

Inventor： Graham Bernard Cunningham ,  Stephen Felix

IPC: H03M13/00 ,  G11C29/42 ,  H03M13/11 ,  H03M13/15 ,  G11C29/12

Abstract: A memory controller is provided for reading and writing to and from a memory module. The memory controller implements an error correction algorithm, which calculates error correction code for message data to be written to the memory module and checks the error correction code against the message data when the data is read out of the memory module. The memory controller spreads each codeword over at least four different beats sent over the interface with the memory module, with each beat comprising a symbol of error correction code. Bits of a particular symbol of message data occupy the same positions in different beats. Since the bits of the symbols occupy the same positions in different beat, the number of bits affected by a hardware error is minimised. With four symbols of error correction code available for use in the codeword.

公开(公告)号：US11449254B1

公开(公告)日：2022-09-20

申请号：US17024357

申请日：2020-09-17

Applicant: Graphcore Limited

Inventor： Richard Osborne ,  Chad Jarvis ,  Fabian Tschopp ,  Tim Hutt ,  Emmanuel Menage

IPC: G06F3/06 ,  G06F8/41 ,  G06N3/04

Abstract: A system and method for providing a set of data transfer instructions for converting one or more tensors between two different layouts. A first layout is used for storage of the data in host memory. A second layout is used for storage of the data in external memory accessible to a subsystem. The subsystem acts as a work accelerator to the host, and reads the external memory and processes the data read from the external memory. The first layout may be a logical representation of the tensor. The second layout is optimised for transfer to and processing by the subsystem. The data transfer instructions for converting between the two layouts are generated in dependence upon an analysis of the instructions to be executed by the subsystem.

公开(公告)号：US20220197645A1

公开(公告)日：2022-06-23

申请号：US17654449

申请日：2022-03-11

Applicant: Graphcore Limited

Inventor： Alan Graham ALEXANDER ,  Simon Christian KNOWLES ,  Mrudula Chidambar GORE ,  Jonathan FERGUSON

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

Abstract: A processor is disclosed including: a barrel-threaded execution unit for executing concurrent threads, and a repeat cache shared between the concurrent threads. The processor's instruction set includes a repeat instruction which takes a repeat count operand. When the repeat cache is not claimed and the repeat instruction is executed in a first thread, a portion of code is cached from the first thread into the repeat cache, the state of the repeat cache is changed to record it as claimed, and the cached code is executed a number of times. When the repeat instruction is then executed in a further thread, then the already-cached portion of code is again executed a respective number of times, each time from the repeat cache. For each of the first and further instructions, the repeat count operand in the respective instruction specifies the number of times to execute the cached code.

公开(公告)号：US11281506B2

公开(公告)日：2022-03-22

申请号：US17165513

申请日：2021-02-02

Applicant: Graphcore Limited

Inventor： Brian Manula ,  Harald Hoeg ,  Ola Torudbakken

IPC: G06F9/54 ,  G06F9/455

Abstract: A system comprising a gateway for interfacing external data sources with one or more accelerators. The gateway comprises a plurality of virtual gateways, each of which is configured to stream data from the external data sources to one or more associated accelerators. The plurality of virtual gateways are each configured to stream data from external data sources so that the data is received at an associated accelerator in response to a synchronisation point being obtained by a synchronisation zone. Each of the virtual gateways is assigned a virtual ID so that when data is received at the gateway, data can be delivered to the appropriate gateway.

公开(公告)号：US11263017B2

公开(公告)日：2022-03-01

申请号：US17323539

申请日：2021-05-18

Applicant: Graphcore Limited

Inventor： James Pallister ,  Jamie Hanlon

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor includes: memory; an execution pipeline having a plurality of pipeline stages configured to process data provided to the execution pipeline and to store a result of the processing into the memory; a receive pipeline having a plurality of pipeline stages configured to handle incoming data to the processor and storing the incoming data into memory; context status storage configured to hold an exception indicator of an exception encountered by the execution pipeline while the execution pipeline processes data; wherein the receive pipeline is configured to determine that an exception has been committed to the context status storage by the execution pipeline, to suppress a write to memory of any incoming data to be handled by the receive pipeline and to commit a corresponding exception indicator to the context status storage at a final one of its pipeline stages.

公开(公告)号：US11258699B2

公开(公告)日：2022-02-22

申请号：US16841754

申请日：2020-04-07

Applicant: Graphcore Limited

Inventor： Lars Paul Huse

IPC: H04L12/707 ,  H04L45/24 ,  H04L1/22 ,  H04L12/40 ,  H04L12/54 ,  H04L45/00 ,  H04L45/28 ,  H04L12/70

Abstract: The provision of redundancy in a sync network, which protects the sync network against faults, such as broken cables in the sync network. The gateway comprises a sync propagation module configured to provide redundant sync requests that are sent along different pathways in the sync network. These sync requests are sent to towards different masters in the sync network. If a fault occurs at a point in one of the paths, the gateway will still receive a sync acknowledgment returned along the other path. Furthermore, the use of redundant sync networks, propagating the sync requests across different paths, allows fault detection in the wiring to be detected.

公开(公告)号：US20220019487A1

公开(公告)日：2022-01-20

申请号：US17338898

申请日：2021-06-04

Applicant: Graphcore Limited

Inventor： Ola TORUDBAKKEN ,  Wei-Lin GUAY

IPC: G06F9/52 ,  G06F9/54 ,  G06F9/38

Abstract: A host system compiles a set of local programs which are provided over a network to a plurality of subsystems. By defining the synchronisation activity on the host, and then providing that information to the subsystems, the host can service a large number of subsystems. The defined synchronisation activity includes defining the synchronisation groups between which synchronisation barriers occur and the points during program execution at which data exchange with the host occurs. Defining synchronisation activity between the subsystems allows a large number of subsystems to be connecting whilst minimising the required exchanges with the host.