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公开(公告)号：US11675686B2
公开(公告)日：2023-06-13
申请号：US17445550
申请日：2021-08-20
Applicant: Graphcore Limited
CPC classification number: G06F11/349 , G06F13/4068
Abstract: A device comprising: a bus forming a ring path for circulation of one or more data packets around the bus, wherein the one or more data packets comprises a trace report packet for collecting trace data from a plurality of components attached to the bus, wherein the bus is configured to repeatedly circulate the trace report packet with a fixed time period taken for each circulation of the ring path performed by the trace report packet; and the plurality of components, each of which comprises circuitry configured to, upon reception of the trace report packet at the respective component, insert one or more items of the trace data that have been obtained by the respective component.
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公开(公告)号：US20190354494A1
公开(公告)日：2019-11-21
申请号：US16525833
申请日：2019-07-30
Applicant: Graphcore Limited
Inventor： Daniel John Pelham Wilkinson , Richard Luke Southwell Osborne , Stephen Felix , Graham Bernard Cunningham , Alan Graham Alexander
Abstract: A system comprising an arrangement of multiple processor modules, and an external interconnect for communicating data in the form of packets to outside the arrangement. The interconnect comprises an exchange block configured to provide flow control. One of the processor modules is arranged to send an exchange request message to the exchange block on behalf of others with data to send outside the arrangement. The exchange block sends an exchange-on message to a first of these processor modules, to cause the first module to start sending packets via the interconnect. Then, once this processor module has sent its last data packet, the exchange block sends an exchange-off message to this processor module to cause it to stop sending packets, and sends another exchange-on message to the next processor module with data to send, and so forth.
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公开(公告)号：US11775415B2
公开(公告)日：2023-10-03
申请号：US16527454
申请日：2019-07-31
Applicant: Graphcore Limited
Inventor： Alan Graham Alexander , Graham Bernard Cunningham
CPC classification number: G06F11/366 , G06F9/30101 , G06F9/30123 , G06F9/3802 , G06F9/3814 , G06F9/3851 , G06F9/3867 , G06F9/48
Abstract: A processor comprising at least one processing module, each processing module comprising: an execution pipeline; memory; an instruction fetch unit comprising operable to switch between an operational mode and a debugging mode, the instruction fetch unit being configured so as, when in the operational mode, to fetch machine code instructions from the memory into the execution pipeline to be executed; and a debug interface for connecting to a debug adapter. The debug interface comprises a debug instruction register enabling the debug adapter to write a machine code instruction to the debug instruction register, and wherein the instruction fetch unit is configured so as, when in the debug mode, to fetch instructions from the debug instruction register into the pipeline instead of from the memory.
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公开(公告)号：US11681642B2
公开(公告)日：2023-06-20
申请号：US17328143
申请日：2021-05-24
Applicant: Graphcore Limited
IPC: G06F13/374 , G06F13/364 , G06F15/173
CPC classification number: G06F13/374 , G06F13/364 , G06F15/17375
Abstract: A device comprising: a control bus; a plurality of requesting circuits each accessible on the control bus, wherein each of the plurality of requesting circuits is operable to dispatch read or write requests to the control bus for delivery to at least one of a plurality of receiving circuits, and the plurality of receiving circuits each accessible on the control bus, and each of which is operable to receive requests from the at least one control bus and service the requests by providing at least one of read or write access to storage associated with the respective receiving circuit, wherein the control bus provides a ring path configured to support, the requests in circulation in the ring path, wherein the control bus is configured to propagate each of at least some of the requests at least until those requests have been serviced by at least one of the receiving circuits.
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公开(公告)号：US11462293B2
公开(公告)日：2022-10-04
申请号：US17443061
申请日：2021-07-20
Applicant: Graphcore Limited
Inventor： Graham Bernard Cunningham , Stephen Felix
Abstract: A memory controller is provided for reading and writing to and from a memory module. The memory controller implements an error correction algorithm, which calculates error correction code for message data to be written to the memory module and checks the error correction code against the message data when the data is read out of the memory module. The memory controller spreads each codeword over at least four different beats sent over the interface with the memory module, with each beat comprising a symbol of error correction code. Bits of a particular symbol of message data occupy the same positions in different beats. Since the bits of the symbols occupy the same positions in different beat, the number of bits affected by a hardware error is minimised. With four symbols of error correction code available for use in the codeword.
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Patent Agency Ranking
公开(公告)号：US11726937B2
公开(公告)日：2023-08-15
申请号：US17447832
申请日：2021-09-16
Applicant: Graphcore Limited
Inventor： Graham Bernard Cunningham , Stephen Felix
IPC: G06F13/364 , G06F9/52 , G06F13/40
CPC classification number: G06F13/364 , G06F9/522 , G06F13/4059
Abstract: A method for controlling the sending of data by a plurality of processors belonging to a device, the method comprising: sending a first message to a first processor of the plurality of processors to grant permission to the first processor of the plurality of processors to send a first set of data packets over at least one external interface of the device; receiving from the first processor, an identifier of a second processor of the plurality of processors; and in response to receipt of the identifier of the second processor, send a second message to the second processor to grant permission to the second processor to send a second set of data packets over the at least one external interface.
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公开(公告)号：US20200319991A1
公开(公告)日：2020-10-08
申请号：US16527454
申请日：2019-07-31
Applicant: Graphcore Limited
Inventor： Alan Graham Alexander , Graham Bernard Cunningham
Abstract: A processor comprising at least one processing module, each processing module comprising: an execution pipeline; memory; an instruction fetch unit comprising operable to switch between an operational mode and a debugging mode, the instruction fetch unit being configured so as, when in the operational mode, to fetch machine code instructions from the memory into the execution pipeline to be executed; and a debug interface for connecting to a debug adapter. The debug interface comprises a debug instruction register enabling the debug adapter to write a machine code instruction to the debug instruction register, and wherein the instruction fetch unit is configured so as, when in the debug mode, to fetch instructions from the debug instruction register into the pipeline instead of from the memory.
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公开(公告)号：US10558595B2
公开(公告)日：2020-02-11
申请号：US16165607
申请日：2018-10-19
Applicant: Graphcore Limited
Inventor： Daniel John Pelham Wilkinson , Richard Luke Southwell Osborne , Stephen Felix , Graham Bernard Cunningham , Alan Graham Alexander
IPC: G06F13/20 , G06F13/42 , G06F15/16 , G06F15/163
Abstract: A processor comprising multiple tiles on the same chip, and an external interconnect for communicating data off-chip in the form of packets. The external interconnect comprises an external exchange block configured to provide flow control and queuing of the packets. One of the tiles is nominated by the compiler to send an external exchange request message to the exchange block on behalf of others with data to send externally. The exchange sends an exchange-on message to a first of these tiles, to cause the first tile to start sending packets via the external interconnect. Then, once this tile has sent its last data packet, the exchange block sends an exchange-off control packet to this tile to cause it to stop sending packets, and sends another exchange-on message to the next tile with data to send, and so forth.
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公开(公告)号：US11822427B2
公开(公告)日：2023-11-21
申请号：US17823131
申请日：2022-08-30
Applicant: Graphcore Limited
Inventor： Stephen Felix , Daniel Wilkinson , Graham Bernard Cunningham
CPC classification number: G06F11/1068 , G06F11/0772 , G06F11/1004 , H03K19/21
Abstract: Signature generation circuitry is configured to update a signature in response to each of a plurality of writes to memory. The signature is updated by performing bitwise operations between current bit values of the signature and at least some of the bits written to memory in response a write. The bitwise operation are order-independent such that the resulting signature is the same irrespective of the order in which the writes are used to update the signature. The signatures are formed in an order-independent manner such that, if no errors have occurred in generating the data to be written to be memory, the signatures will match. In this way, a compact signature is developed that is suitable export from the data processing device for checking against a corresponding data processing device of a machine running a duplicate application.
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公开(公告)号：US11520941B2
公开(公告)日：2022-12-06
申请号：US17328739
申请日：2021-05-24
Applicant: Graphcore Limited
Abstract: Access permissions are set for different requesting circuits on a control bus. The access permissions can be set by the level 1 manager and the level 2 manager, allowing two layers of security to be added. The level 1 manager has priority, allowing it to add access permissions that cannot be removed by the level 2 manager.
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