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31 条记录 (耗时 0.017 秒)

    Partial CRC insertion in data packets for early forwarding
    22.
    发明授权
    Partial CRC insertion in data packets for early forwarding 有权
    数据包中的部分CRC插入用于提前转发

    公开(公告)号：US07840873B2

    公开(公告)日：2010-11-23

    申请号：US11610219

    申请日：2006-12-13

    申请人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    发明人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    IPC分类号： H03M13/00

    CPC分类号： H04L1/0061 ,  H04L1/0079 ,  H04L1/1829 ,  H04L2001/0097

    摘要： In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.

    摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上发送的分组，所述分组包括命令和相关联的分组数据。 耦合到分组调度器并且被配置为在链路上传送分组，并且接口电路被配置为生成覆盖分组的错误检测数据。 接口电路被配置为在分组的末尾发送覆盖分组的错误检测数据，并且还被配置为在分组内插入至少一个部分错误检测数据。 部分错误检测数据覆盖部分错误检测数据之前的分组的一部分。 接收机被配置为接收数据并基于部分CRC校验转发数据。

    Data resynchronization
    24.
    发明授权
    Data resynchronization 失效
    数据重新同步

    公开(公告)号：US5652758A

    公开(公告)日：1997-07-29

    申请号：US680409

    申请日：1996-07-15

    申请人： Greggory D. Donley

    发明人： Greggory D. Donley

    IPC分类号： H04J3/06 ,  H04L12/42

    CPC分类号： H04J3/0685 ,  H04J3/062 ,  H04L12/422

    摘要： An array of digital data processing nodes arrayed in at least one node-ring where each node has its own transmission-clock which is approximately the same frequency as the transmission-clock of other nodes in the ring and where data is transferred in data-packets, the combination therewith of data-transmission-resynchronizing stage comprising a "circular FIFO" arrangement.

    摘要翻译： 排列在至少一个节点环中的数字数据处理节点阵列，其中每个节点具有其自身的传输时钟，其频率与环中其他节点的传输时钟大致相同，并且数据在数据包中传输 与数据传输 - 再同步级的组合包括“循环FIFO”排列。

    QUEUE FREEZE ON PROTOCOL ERROR
    26.
    发明申请
    QUEUE FREEZE ON PROTOCOL ERROR 有权
    QUEUE冻结协议错误

    公开(公告)号：US20120151251A1

    公开(公告)日：2012-06-14

    申请号：US12963086

    申请日：2010-12-08

    申请人： Greggory D. Donley

    发明人： Greggory D. Donley

    IPC分类号： G06F11/08

    CPC分类号： G06F11/079 ,  G06F11/0724

    摘要： A method and apparatus for retrieving a state of a processor at a time at which failure is detected. More specifically, the detection of one or more protocol errors results in the halting of operations of one or more system elements, and the retrieving of the state of the processor at the time of the failure.

    摘要翻译： 一种用于在检测到故障的时间检索处理器的状态的方法和装置。 更具体地，检测到一个或多个协议错误导致停止一个或多个系统元件的操作，以及在故障时检索处理器的状态。

    METHOD AND APPARATUS FOR HANDLING EXCESS DATA DURING MEMORY ACCESS
    27.
    发明申请
    METHOD AND APPARATUS FOR HANDLING EXCESS DATA DURING MEMORY ACCESS 有权
    在存储器访问期间处理超时数据的方法和装置

    公开(公告)号：US20090031088A1

    公开(公告)日：2009-01-29

    申请号：US11828382

    申请日：2007-07-26

    申请人： Greggory D. Donley

    发明人： Greggory D. Donley

    IPC分类号： G06F12/16

    CPC分类号： G06F12/0862 ,  G06F12/127

    摘要： A computer system includes a system memory and a processor having one or more processor cores and a memory controller. The memory controller may control data transfer to the system memory. The processor further includes a cache memory such as an L3 cache, for example, that includes a data storage array for storing blocks of data. In response to a request for data by a given processor core, the system memory may provide a first data block that corresponds to the requested data, and an additional data block that is associated with the first data block and that was not requested by the given processor core. In addition, the memory controller may provide the first data block to the given processor core and store the additional data block in the cache memory.

    摘要翻译： 计算机系统包括系统存储器和具有一个或多个处理器核心和存储器控制器的处理器。 存储器控制器可以控制到系统存储器的数据传输。 处理器还包括例如包括用于存储数据块的数据存储阵列的诸如L3高速缓存的高速缓冲存储器。 响应于给定处理器核心对数据的请求，系统存储器可以提供对应于所请求数据的第一数据块，以及与第一数据块相关联并且未被给定的请求的附加数据块 处理器核心。 此外，存储器控制器可以将第一数据块提供给给定的处理器核，并将附加数据块存储在高速缓冲存储器中。

    APPARATUS FOR REDUCING CACHE LATENCY WHILE PRESERVING CACHE BANDWIDTH IN A CACHE SUBSYSTEM OF A PROCESSOR
    28.
    发明申请
    APPARATUS FOR REDUCING CACHE LATENCY WHILE PRESERVING CACHE BANDWIDTH IN A CACHE SUBSYSTEM OF A PROCESSOR 审中-公开
    用于在处理器的缓存子系统中保存缓存带宽时减少高速缓存的设备

    公开(公告)号：US20090006777A1

    公开(公告)日：2009-01-01

    申请号：US11769970

    申请日：2007-06-28

    申请人： Greggory D. Donley ,  William A. Hughes

    发明人： Greggory D. Donley ,  William A. Hughes

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0897 ,  G06F12/0895 ,  G06F2212/1016

    摘要： A processor cache memory subsystem includes a cache controller coupled to a tag logic unit. The cache controller may monitor read request resources associated with the cache subsystem and receive read requests for data stored in a data storage array of the cache subsystem. The tag logic unit may determine whether one or more requested address bits match any address tag stored within a tag array of the cache subsystem. The cache controller may, in response to determining the read request resources associated with the cache subsystem are available, selectably send the request for data with an implicit request indication being asserted. In response to determining the read request resources associated with the cache subsystem are not available, the cache controller may send the request for data without an implicit request indication being asserted.

    摘要翻译： 处理器高速缓存存储器子系统包括耦合到标签逻辑单元的高速缓存控制器。 高速缓存控制器可以监视与高速缓存子系统相关联的读取请求资源，并且接收对存储在高速缓存子系统的数据存储阵列中的数据的读取请求。 标签逻辑单元可以确定一个或多个所请求的地址位是否匹配存储在高速缓存子系统的标签阵列内的任何地址标签。 响应于确定与高速缓存子系统相关联的读取请求资源可用，高速缓存控制器可以可选择地发送具有被断言的隐式请求指示的数据请求。 响应于确定与高速缓存子系统相关联的读取请求资源不可用，高速缓存控制器可以发送对数据的请求，而不会隐式地请求指示。

    CACHE MEMORY HAVING CONFIGURABLE ASSOCIATIVITY
    29.
    发明申请
    CACHE MEMORY HAVING CONFIGURABLE ASSOCIATIVITY 审中-公开
    具有可配置关联性的高速缓存存储器

    公开(公告)号：US20090006756A1

    公开(公告)日：2009-01-01

    申请号：US11771299

    申请日：2007-06-29

    申请人： Greggory D. Donley

    发明人： Greggory D. Donley

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0864 ,  G06F12/0846 ,  G06F2212/601 ,  Y02D10/13

    摘要： A processor cache memory subsystem includes a cache memory having a configurable associativity. The cache memory may operate in a fully associative addressing mode and a direct addressing mode with reduced associativity. The cache memory includes a data storage array including a plurality of independently accessible sub-blocks for storing blocks of data. For example each of the sub-blocks implements an n-way set associative cache. The cache memory subsystem also includes a cache controller that may programmably select a number of ways of associativity of the cache memory. When programmed to operate in the fully associative addressing mode, the cache controller may disable independent access to each of the independently accessible sub-blocks and enable concurrent tag lookup of all independently accessible sub-blocks, and when programmed to operate in the direct addressing mode, the cache controller may enable independent access to one or more subsets of the independently accessible sub-blocks.

    摘要翻译： 处理器高速缓存存储器子系统包括具有可配置的关联性的高速缓冲存储器。 缓存存储器可以以完全关联寻址模式和具有降低的关联性的直接寻址模式来操作。 高速缓存存储器包括数据存储阵列，其包括用于存储数据块的多个可独立访问的子块。 例如，每个子块实现n路组关联高速缓存。 高速缓存存储器子系统还包括高速缓存控制器，该缓存控制器可以可编程地选择高速缓冲存储器的多个关联方式。 当被编程为以完全关联寻址模式操作时，高速缓存控制器可以禁用对每个可独立访问的子块的独立访问，并且启用所有可独立访问的子块的并发标签查找，并且当被编程为以直接寻址模式操作时 ，高速缓存控制器可以实现对独立可访问的子块的一个或多个子集的独立访问。

    Resynchronization of data
    30.
    发明授权
    Resynchronization of data 失效
    数据重新同步

    公开(公告)号：US6081538A

    公开(公告)日：2000-06-27

    申请号：US895818

    申请日：1997-07-17

    申请人： Greggory D. Donley

    发明人： Greggory D. Donley

    IPC分类号： H04J3/06 ,  H04L12/42

    CPC分类号： H04J3/0685 ,  H04J3/062 ,  H04L12/422

    摘要： A network node for receiving a packet of data written from the network and providing the packet to the network. The packet of data includes first data received from the network in response to a first clock signal and second data provided to the network in response to a second clock signal. The node is adapted to compensate for a drift between the first clock signal and the second clock signal. The node includes a first counter that receives the first clock signal and produces a write-point signal in response to the first clock signal. The node also includes a plurality of registers arranged in a wrap-around configuration, with a first one of the registers coupled to be selected by the write-point signal to receive the first data from the network. A second counter receives the second clock signal and produces a read-point signal in response to the second clock signal, with a further register being selected by the read-point signal to provide the second data to the network. A comparison block receives the read-point signal and the write-point signal and compares the read-point signal and the write-point signal to detect the drift between the first clock signal and the second clock signal, and generates an output signal representing the drift. A control block receives the output signal from the comparison block and generates a signal to the second counter to adjust the read-point signal to compensate for the drift between the first and the second clock signals.

    摘要翻译： 一个网络节点，用于接收从网络写入的数据包，并将数据包提供给网络。 数据包包括响应于第一时钟信号从网络接收的第一数据和响应于第二时钟信号提供给网络的第二数据。 节点适于补偿第一时钟信号和第二时钟信号之间的漂移。 节点包括接收第一时钟信号并响应于第一时钟信号产生写入点信号的第一计数器。 该节点还包括以卷绕配置布置的多个寄存器，其中第一个寄存器被耦合以由写入点信号选择以从网络接收第一数据。 第二计数器接收第二时钟信号并响应于第二时钟信号产生读点信号，另外的寄存器由读点信号选择，以向网络提供第二数据。 比较块接收读点信号和写点信号，并比较读点信号和写点信号，以检测第一时钟信号和第二时钟信号之间的漂移，并产生一个表示 漂移。 控制块从比较块接收输出信号，并向第二计数器产生一个信号，以调整读点信号以补偿第一和第二时钟信号之间的漂移。