公开(公告)号：US20140169495A1

公开(公告)日：2014-06-19

申请号：US14232479

申请日：2011-08-01

Applicant: Mathieu Lesbats ,  Hubert Bode ,  Rafael Pena Bello

Inventor： Mathieu Lesbats ,  Hubert Bode ,  Rafael Pena Bello

IPC: H04L25/02

CPC classification number: H04L25/02 ,  H03K19/00361 ,  H03K19/017509

Abstract: A signalling circuit for a signal channel of a communication network comprises a communication network terminal connectable to the signal channel and to a voltage supply; an input terminal connectable to receive a transmit signal; a driver device comprising a first driver terminal connected to the communication network terminal, a second driver terminal connected to ground, and a driver control terminal connected to the input terminal; wherein the driver device is arranged to connect the communication network terminal to ground in response to a transition from a low to a high voltage driver control signal state of a driver control signal received at the driver control terminal. And the signalling circuit comprises a feedback circuit connected to the first driver terminal and the driver control terminal and comprising a capacitive device; and a pull-down device arranged to connect the driver control terminal to ground after a predefined delay after a transition of the transmit signal from a low to a high voltage transmit signal state.

Abstract translation: 用于通信网络的信号信道的信令电路包括可连接到信号信道和电压源的通信网络终端; 可接收发送信号的输入端子; 驱动器装置，包括连接到通信网络终端的第一驱动器端子，连接到地的第二驱动器端子和连接到输入端子的驱动器控制端子; 其中所述驱动器装置被布置成响应于从所述驾驶员控制终端处接收到的驾驶员控制信号的低电压到高电压驱动器控制信号状态的转变而将所述通信网络终端连接到地。 并且信令电路包括连接到第一驱动器端子和驱动器控制端子并包括电容性装置的反馈电路; 以及下拉装置，其被布置成在所述发射信号从低电压到高电压发射信号状态的转变之后在预定义的延迟之后将所述驱动器控制端子接地。

公开(公告)号：US20140035638A1

公开(公告)日：2014-02-06

申请号：US14111775

申请日：2011-04-20

Applicant: Hubert Bode

Inventor： Hubert Bode

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/183 ,  H03L7/1974

Abstract: A clock signal generation system is provided that includes a clock signal generating circuit arranged to provide a first clock signal having a selectable first clock rate; a divider circuit connected to receive the first clock signal and arranged to generate, depending on a division factor, a second clock signal from the first clock signal, having a constant second clock rate and being synchronized with the first clock signal; and a controller module connected to the divider circuit and arranged to change the division factor when a different first clock rate is selected, to keep the second clock rate constant and the second clock signal synchronized with the first clock signal.

Abstract translation: 提供了一种时钟信号发生系统，其包括时钟信号发生电路，其被布置为提供具有可选择的第一时钟速率的第一时钟信号; 分频器电路，被连接以接收第一时钟信号，并且被布置为根据分频因子产生具有恒定的第二时钟速率并与第一时钟信号同步的来自第一时钟信号的第二时钟信号; 以及控制器模块，连接到分频器电路，并且被布置为当选择不同的第一时钟速率时改变分频因子，以保持第二时钟速率恒定，并且第二时钟信号与第一时钟信号同步。

公开(公告)号：US08605398B2

公开(公告)日：2013-12-10

申请号：US13389179

申请日：2009-08-06

Applicant: Hubert Bode ,  Mauro Giacomini

Inventor： Hubert Bode ,  Mauro Giacomini

IPC: H02H3/22

CPC classification number: H01L27/0285 ,  H03K19/00315

Abstract: An electronic device comprises an application circuit; a first supply rail having a first electric potential; a second supply rail having a second electric potential different from the first electric potential; at least one terminal having a third electric potential, connected to the application circuit; and a protection circuit for protecting the application circuit from an injected current. The protection circuit comprises a first conductive line connected between the at least one terminal and the first supply rail, the first conductive line comprising a first switch having a first control input; and a first voltage amplifier circuit having a first input connected to the at least one terminal, a second input connected to the second supply rail and a first output connected to the first control input.

Abstract translation: 电子设备包括应用电路; 具有第一电位的第一供电轨; 具有不同于第一电位的第二电位的第二供电轨; 具有第三电位的至少一个端子，连接到所述应用电路; 以及用于保护施加电路免受注入电流的保护电路。 所述保护电路包括连接在所述至少一个端子和所述第一电源轨之间的第一导线，所述第一导线包括具有第一控制输入的第一开关; 以及第一电压放大器电路，其具有连接到所述至少一个端子的第一输入端，连接到所述第二电源轨道的第二输入端和连接到所述第一控制输入端的第一输出端。

公开(公告)号：US20110297935A1

公开(公告)日：2011-12-08

申请号：US13201977

申请日：2009-02-23

Applicant: Hubert Bode ,  Andreas Laudenbach ,  Andreas Roth

Inventor： Hubert Bode ,  Andreas Laudenbach ,  Andreas Roth

IPC: H01L23/58

CPC classification number: H01L23/585 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device comprises a substrate provided with a doping of a first type, on which an electronic circuit is provided surrounded by a circuit portion of the substrate provided with a doping of a second type; at least one pad for connecting the electronic circuit to an external device outside the substrate, surrounded by a pad portion provided with a doping of the second type; a sensing device comprising a sensor portion of the substrate provided with a doping of the first type, for sensing a parameter forming a measure for a local electrical potential of the substrate; and an evaluation unit connected to the sensing device, for providing an evaluation signal based on a difference between the parameter and a reference value.

Abstract translation: 半导体器件包括设置有第一类型的掺杂的衬底，电子电路设置在其上，由设置有第二类型的掺杂的衬底的电路部分围绕; 至少一个焊盘，用于将所述电子电路连接到所述衬底外部的外部设备，由被提供有所述第二类型的掺杂的焊盘部分围绕; 感测装置，包括设置有第一类型的掺杂的衬底的传感器部分，用于感测形成衬底的局部电势的度量的参数; 以及评估单元，连接到感测装置，用于基于参数和参考值之间的差异提供评估信号。

公开(公告)号：US20100164569A1

公开(公告)日：2010-07-01

申请号：US12664028

申请日：2007-06-14

Applicant: Hubert Bode ,  Andreas Laudenbach ,  Andreas Roth ,  Engelbert Wittich

Inventor： Hubert Bode ,  Andreas Laudenbach ,  Andreas Roth ,  Engelbert Wittich

IPC: H03L7/06 ,  H03L7/00 ,  H03K5/1252

CPC classification number: H03K5/1252

Abstract: A circuit arrangement for detecting unwanted signals on a clock signal comprises an input for receiving the clock signal, and a Phase Lock Loop PLL circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal and an output for providing a PLL output signal. The circuit arrangement further comprises a detector coupled to the output of the PLL circuit and to the input of the circuit arrangement. The detector is arranged to identify correct transitions in the clock signal using the PLL output signal, and to remove incorrect transitions due to unwanted signals from the clock signal so as to provide a filtered clock signal at an output of the circuit arrangement.

Abstract translation: 用于检测时钟信号上不想要的信号的电路装置包括用于接收时钟信号的输入端和锁相环PLL电路，其具有耦合到用于接收时钟信号的电路装置的输入端的参考输入端和用于提供时钟信号的输出端 PLL输出信号。 电路装置还包括耦合到PLL电路的输出和电路装置的输入的检测器。 检测器被布置为使用PLL输出信号来识别时钟信号中的正确转换，并且由于来自时钟信号的不期望的信号而去除不正确的转换，以便在电路装置的输出处提供经滤波的时钟信号。