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    Programmable logic device with pipelined DSP slices
    21.
    发明授权
    Programmable logic device with pipelined DSP slices 有权
    可编程逻辑器件，带流水线DSP片

    公开(公告)号：US07467175B2

    公开(公告)日：2008-12-16

    申请号：US11019782

    申请日：2004-12-21

    Applicant: James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    Inventor： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    IPC: G06F7/38

    CPC classification number: H03K19/17736 ,  H03K19/17732

    Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.

    Abstract translation: 描述了可编程逻辑器件（PLD），其具有可以组合的DSP片段，以创建不同大小和复杂度的DSP电路。 根据一些实施例的DSP片段包括可被配置为从零到两个时钟周期引入不同量的延迟的可编程操作数输入寄存器，例如以支持流水线化。 在一个这样的实施例中，每个DSP片包括具有乘法器端口，被乘数端口和产品端口的部分乘积生成器。 乘法器和被乘数端口通过相应的第一和第二操作数输入寄存器连接到操作数输入端口，每个第一和第二操作数输入寄存器能够从零延迟到两个延迟的时钟周期。 在另一个实施例中，至少一个操作数输入寄存器的输出可以连接到下游DSP片的操作数输入寄存器的输入，使得操作数可以在一个或多个片之间传送。

    Structures and methods for implementing ternary adders/subtractors in programmable logic devices
    22.
    发明授权
    Structures and methods for implementing ternary adders/subtractors in programmable logic devices 有权
    在可编程逻辑器件中实现三元加法器/减法器的结构和方法

    公开(公告)号：US07274211B1

    公开(公告)日：2007-09-25

    申请号：US11373700

    申请日：2006-03-10

    Applicant: James M. Simkins ,  Brian D. Philofsky

    Inventor： James M. Simkins ,  Brian D. Philofsky

    IPC: G06F7/38 ,  H03K19/173

    CPC classification number: H03K19/17728 ,  G06F7/5057 ,  G06F7/509

    Abstract: Structures and methods of implementing an adder circuit in a programmable logic device (PLD). The PLD includes dual-output lookup tables (LUTs) and additional programmable logic elements. The adder circuit includes a 3:2 (3 to 2) compressor circuit that maps three input busses into two compressed busses, and a 2-input cascade adder circuit that adds the two compressed busses to yield the final sum bus. The dual-output LUTs implement both the 3:2 compressor circuit and a portion of the 2-input adder. The remaining portion of the 2-input adder is implemented using the additional programmable logic elements of the PLD. In some embodiments, the 3:2 compressor circuit is preceded by an M:3 compressor, which changes the 3-input adder into an M-input adder. In these embodiments, a second input bus is left-shifted with respect to the first input bus, and a third input busses is left-shifted with respect to the second input bus.

    Abstract translation: 在可编程逻辑器件（PLD）中实现加法器电路的结构和方法。 PLD包括双输出查找表（LUT）和其他可编程逻辑元件。 加法器电路包括将三个输入总线映射成两个压缩总线的3：2（3至2）压缩器电路，以及将两个压缩总线相加以产生最终总和的2输入级联加法器电路。 双输出LUT实现3：2压缩器电路和2输入加法器的一部分。 使用PLD的附加可编程逻辑元件来实现2输入加法器的剩余部分。 在一些实施例中，3：2压缩器电路之前是M：3压缩器，其将3输入加法器改变为M输入加法器。 在这些实施例中，第二输入总线相对于第一输入总线左移，第三输入总线相对于第二输入总线左移。

    Digital signal processing block with preadder stage
    24.
    发明授权
    Digital signal processing block with preadder stage 有权
    数字信号处理块，带舞台

    公开(公告)号：US08543635B2

    公开(公告)日：2013-09-24

    申请号：US12360836

    申请日：2009-01-27

    Applicant: James M. Simkins ,  Alvin Y. Ching ,  John M. Thendean ,  Vasisht M. Vadi ,  Chi Fung Poon ,  Muhammad Asim Rab

    Inventor： James M. Simkins ,  Alvin Y. Ching ,  John M. Thendean ,  Vasisht M. Vadi ,  Chi Fung Poon ,  Muhammad Asim Rab

    IPC: G06F7/50 ,  H01L25/00

    CPC classification number: G06F7/5443 ,  H03H17/06 ,  H03H2220/04 ,  H03H2220/06 ,  H03K19/17732

    Abstract: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.

    Abstract translation: 描述了具有用于集成电路的前级的数字信号处理块。 数字信号处理块包括一个前级和一个控制总线。 控制总线耦合到前级，用于动态地控制前级的操作。 前级级包括：耦合到控制总线的第一多路复用器的第一输入端口; 耦合到控制总线的第一逻辑门的第二输入端口; 耦合到控制总线的第二逻辑门的​​第三输入端口; 以及耦合到控制总线的加法器/减法器的第四输入端口。

    Method and system for maintaining the security of design information
    25.
    发明授权
    Method and system for maintaining the security of design information 有权
    维护设计信息安全的方法和系统

    公开(公告)号：US08220060B1

    公开(公告)日：2012-07-10

    申请号：US12763465

    申请日：2010-04-20

    Applicant: James M. Simkins

    Inventor： James M. Simkins

    IPC: G06F17/50

    CPC classification number: G06F21/10

    Abstract: Approaches for protecting design information are disclosed. In one approach, a request for an IP core from an integrated circuit device is received, and the request includes identification information. An identifier range is determined from the identification information. The identifier range includes a plurality of unique device identifiers identifying a plurality of integrated circuit devices that are allowed to receive the IP core. The identifier range is downloaded to the integrated circuit device, which evaluates whether or not a unique device identifier that is stored on the integrated circuit device is within the downloaded identifier range. The IP core is programmed into the integrated circuit in response to the unique device identifier that is stored on the integrated circuit device being within the downloaded identifier range.

    Abstract translation: 公开了保护设计信息的方法。 在一种方法中，接收到来自集成电路设备的IP核的请求，并且该请求包括识别信息。 从识别信息确定标识符范围。 标识符范围包括识别允许接收IP核的多个集成电路设备的多个唯一设备标识符。 标识符范围被下载到集成电路设备，其评估存储在集成电路设备上的唯一设备标识符是否在下载的标识符范围内。 响应于存储在下载的标识符范围内的集成电路设备上的唯一设备标识符，将IP内核编程到集成电路中。

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