Communication unit for a person's skin
    22.
    发明授权
    Communication unit for a person's skin 有权
    沟通单位为人的皮肤

    公开(公告)号:US09082268B2

    公开(公告)日:2015-07-14

    申请号:US11597730

    申请日:2005-05-26

    CPC classification number: G08B6/00 G08B21/24

    Abstract: An electric communication unit to be placed on a person's skin. The electric communication unit includes a support element, a series of body contacts, and a pulse generator. The pulse generator generates a series of pulses and transmits the series of pulses to the series of body contacts, the series of body contacts being provided to transmit the series of pulses onto the skin of the person. The electric communication unit is in the form of a patch.

    Abstract translation: 一个放置在人皮肤上的电子通信单元。 电气通信单元包括支撑元件,一系列主体触点和脉冲发生器。 脉冲发生器产生一系列脉冲并将一系列脉冲发送到一系列身体接触,提供一系列身体接触以将一系列脉冲传送到人的皮肤上。 电气通信单元是补丁的形式。

    High Speed Edge Card Connector
    23.
    发明申请
    High Speed Edge Card Connector 有权
    高速边缘卡连接器

    公开(公告)号:US20130309906A1

    公开(公告)日:2013-11-21

    申请号:US13993438

    申请日:2011-12-13

    Applicant: Jan De Geest

    Inventor: Jan De Geest

    CPC classification number: H01R13/646 H01R12/721 H01R13/6477

    Abstract: A connector for connection between a circuit board and a further electronic component is disclosed. The connector includes an insulating housing having a board slot open towards a mating direction for accommodating the circuit board, and a plurality of terminals. The terminals have a rear portion, an intermediate portion and a tip portion, the intermediate portion including a contact portion for contacting a surface portion of the circuit board when accommodated in the board slot. The housing includes a window such that for a number of adjacent terminals housing material is absent between the intermediate portions. A shield member may be arranged in between the rear portions of the terminals. Improved circuit boards are also disclosed.

    Abstract translation: 公开了一种用于电路板和另一电子部件之间连接的连接器。 连接器包括绝缘壳体,其具有朝向配合方向开口的板槽,用于容纳电路板,以及多个端子。 端子具有后部,中间部分和尖端部分,中间部分包括接触部分,用于在容纳在板槽中时接触电路板的表面部分。 壳体包括一个窗口,使得对于多个相邻的端子,在中间部分之间不存在壳体材料。 可以在端子的后部之间布置屏蔽构件。 还公开了改进的电路板。

    SIGNAL TRANSMISSION FOR HIGH SPEED INTERCONNECTIONS
    25.
    发明申请
    SIGNAL TRANSMISSION FOR HIGH SPEED INTERCONNECTIONS 有权
    用于高速互连的信号传输

    公开(公告)号:US20110318962A1

    公开(公告)日:2011-12-29

    申请号:US13166155

    申请日:2011-06-22

    Applicant: Jan De Geest

    Inventor: Jan De Geest

    Abstract: A connector assembly includes a substrate and a connector. The substrate includes a ground layer and a trace layer. The substrate defines a substrate edge, and the ground layer defines a ground edge. The connector is mounted on the substrate such that a portion of the connector overhangs the substrate edge of the substrate. The connector includes a first signal contact that defines a mating portion, a mounting portion, a first transition portion connected to the mating portion, and a second transition portion connected to the first transition portion and the mounting portion. The first transition portion of the signal contact at least partially crosses the ground edge such that a gap is defined between the ground edge and the first transition portion and a substantial portion of the second transition portion extends over the gap when the electrical connector is mounted on the substrate.

    Abstract translation: 连接器组件包括基板和连接器。 衬底包括接地层和迹线层。 衬底限定衬底边缘,并且接地层限定接地边缘。 连接器安装在基板上,使得连接器的一部分悬垂在基板的基板边缘上。 连接器包括限定配合部分的第一信号触点,安装部分,连接到配合部分的第一过渡部分和连接到第一过渡部分和安装部分的第二过渡部分。 信号触头的第一过渡部分至少部分地穿过接地边缘,使得在接地边缘和第一过渡部分之间限定间隙,并且当电连接器安装在第一过渡部分上时,第二过渡部分的大部分在间隙上延伸 底物。

    Reducing Suck-Out Insertion Loss
    26.
    发明申请
    Reducing Suck-Out Insertion Loss 有权
    减少吮吸输入损失

    公开(公告)号:US20070279158A1

    公开(公告)日:2007-12-06

    申请号:US11626679

    申请日:2007-01-24

    CPC classification number: H01P3/003

    Abstract: An electrical connector including a lead frame assembly of a first dielectric material that includes a pocket filled with a second dielectric material. A first ground reference, which may be either a ground contact or conductor or a virtual ground defined between signal contacts of a differential signal pair, extends in the first dielectric material and has a first physical length. A second ground reference having a different physical length than the first length extends in the first dielectric material and also through the pocket. The combination of the length of the second ground reference through the pocket along with the difference in the dielectric constants associated with the first and second dielectric materials, provides for equalizing or matching the electrical lengths of these two references having different physical lengths. This may aid in reducing slot-line mode of a co-planar waveguide. The cross-sectional size of the second reference within the pocket may be altered to provide uniform impedance along the length of the second reference as well as an impedance matched to the first conductor.

    Abstract translation: 一种电连接器,包括第一介电材料的引线框架组件,所述引线框架组件包括填充有第二电介质材料的凹穴。 可以是接地触点或导体的第一接地参考或在差分信号对的信号触点之间限定的虚拟接地在第一电介质材料中延伸并且具有第一物理长度。 具有与第一长度不同的物理长度的第二接地参考在第一电介质材料中延伸并且还通过口袋延伸。 通过口袋的第二接地参考的长度与与第一和第二介电材料相关联的介电常数的差异的组合提供均衡或匹配具有不同物理长度的这两个参考物的电长度。 这有助于减小共面波导的槽线模式。 口袋内的第二参考线的横截面尺寸可以改变,以沿着第二参考线的长度提供均匀的阻抗以及与第一导体匹配的阻抗。

    Matched-impedance surface-mount technology footprints
    27.
    发明申请
    Matched-impedance surface-mount technology footprints 有权
    匹配阻抗表面贴装技术的脚印

    公开(公告)号:US20060232301A1

    公开(公告)日:2006-10-19

    申请号:US11287926

    申请日:2005-11-28

    Abstract: Disclosed are methodologies for defining matched-impedance surface-mount technology footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system.

    Abstract translation: 公开了用于在诸如印刷电路板的基板上定义匹配阻抗表面贴装技术足迹的方法,例如适于接收具有端子引线布置的电气部件。 这种覆盖区可以包括导电焊盘的布置和导电通孔的布置。 通孔布置可以不同于衬垫布置。 通孔可以被布置成增加布线密度,同时限制串扰并且提供组件和基板之间的匹配阻抗。 可以改变通孔布置以在板的层上实现期望的布线密度。 增加布线密度可能会减少电路板层数,这往往会降低电容,从而增加阻抗。 接地通路和信号通孔可以以影响阻抗的方式相对于彼此布置。 因此,可以改变通孔布置以实现与部件的阻抗匹配的阻抗。 也可以改变通孔装置以限制相邻信号导体之间的串扰。 因此,可以定义通孔布置以平衡系统的阻抗,串扰和布线密度要求。

    Adaptive Multidimensional model for general electrical interconnection structures by optimizing orthogonal expansion parameters
    28.
    发明授权
    Adaptive Multidimensional model for general electrical interconnection structures by optimizing orthogonal expansion parameters 有权
    通过优化正交扩展参数的一般电互连结构的自适应多维模型

    公开(公告)号:US06295635B1

    公开(公告)日:2001-09-25

    申请号:US09193296

    申请日:1998-11-17

    CPC classification number: G06F17/5036

    Abstract: A method for modeling a general passive interconnection structure for use in a circuit simulator. The model is based on full-wave EM simulations and has a predefined accuracy when compared to the full-wave EM simulator. The interconnection structure is described by parameters that depend on geometric parameters determined by a vector x and the frequency of the signal passing through the interconnect circuit. In a CAD system according to the present invention, information representing a plurality of coefficients, Cm(f) is stored in the CAD system for m=0 to M. The CAD system also stores information specifying the values of a plurality of multinomial functions, Pm(x) for m=0 to M, wherein M>1. When the CAD system needs the value of one of the parameters that describes the interconnect circuit, the CAD system computes an approximation, M(f,x), to that parameter according to the relationship: M ⁡ ( f , x ) = ∑ m = 0 M ⁢ C m ⁡ ( f ) ⁢ P m ⁡ ( x ) . wherein each Pm(x) is a multinomial for m>0. The algorithm combines three adaptive loops. The first adaptive loop selects the required data points by evaluating a number of selection criteria. The number of data points needed to achieve the desired accuracy for the model is minimized. The selected scattering parameters at the data points are calculated using, the full-wave EM simulator. The second adaptive loop selects the frequency points needed by the simulator to accurately model the behavior of the scattering parameters over the whole frequency range. The third adaptive loop selects the number of polynomials needed to accurately model the data points. The resulting model has a predefined accuracy when compared to full-wave EM simulations.

    Abstract translation: 一种用于在电路仿真器中使用的通用无源互连结构建模的方法。 该模型基于全波EM模拟,与全波EM模拟器相比具有预定义的精度。 互连结构由取决于由矢量x确定的几何参数和通过互连电路的信号的频率的参数描述。 在根据本发明的CAD系统中,表示多个系数Cm(f)的信息被存储在用于m = 0到M的CAD系统中.CAD系统还存储指定多个多项函数的值的信息, P m(x)对于m = 0至M,其中M> 1。 当CAD系统需要描述互连电路的一个参数的值时,CAD系统根据以下关系计算该参数的近似值M(f,x):其中每个Pm(x)是多项式, m> 0。 该算法组合了三个自适应循环。 第一个自适应循环通过评估多个选择标准来选择所需的数据点。 实现模型所需精度所需的数据点数量被最小化。 使用全波EM模拟器计算数据点处的选定散射参数。 第二个自适应环路选择模拟器所需的频率点,以便在整个频率范围内精确地建模散射参数的行为。 第三个自适应循环选择准确建模数据点所需的多项式数。 与全波EM模拟相比,得到的模型具有预定义的准确度。

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