公开(公告)号：US07696000B2

公开(公告)日：2010-04-13

申请号：US11565793

申请日：2006-12-01

Applicant: Yaocheng Liu ,  Subramanian S. Iyer ,  Jinghong Li

Inventor： Yaocheng Liu ,  Subramanian S. Iyer ,  Jinghong Li

IPC: H01L21/00

CPC classification number: H01L29/1054 ,  H01L21/2022 ,  H01L21/26506 ,  H01L29/32 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78696

Abstract: Formation of carbon-substituted single crystal silicon layer is prone to generation of large number of defects especially at high carbon concentration. The present invention provides structures and methods for providing low defect carbon-substituted single crystal silicon layer even for high concentration of carbon in the silicon. According to the present invention, the active retrograde profile in the carbon implantation reduces the defect density in the carbon-substituted single crystal silicon layer obtained after a solid phase epitaxy. This enables the formation of semiconductor structures with compressive stress and low defect density. When applied to semiconductor transistors, the present invention enables N-type field effect transistors with enhanced electron mobility through the tensile stress that is present into the channel.

Abstract translation: 碳取代的单晶硅层的形成容易产生大量的缺陷，特别是在高碳浓度下。 本发明提供即使对于硅中的高浓度碳来提供低缺陷碳取代的单晶硅层的结构和方法。 根据本发明，碳注入中的主动逆行曲线减少了在固相外延后获得的碳取代单晶硅层中的缺陷密度。 这使得能够形成具有压缩应力和低缺陷密度的半导体结构。 当应用于半导体晶体管时，本发明能够通过存在于沟道中的拉伸应力使具有增强的电子迁移率的N型场效应晶体管成为可能。

公开(公告)号：US20080128806A1

公开(公告)日：2008-06-05

申请号：US11565793

申请日：2006-12-01

Applicant: Yaocheng Liu ,  Subramanian S. Iyer ,  Jinghong Li

Inventor： Yaocheng Liu ,  Subramanian S. Iyer ,  Jinghong Li

IPC: H01L29/06 ,  H01L21/336 ,  H01L21/225 ,  H01L29/08

CPC classification number: H01L29/1054 ,  H01L21/2022 ,  H01L21/26506 ,  H01L29/32 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78696

Abstract: Formation of carbon-substituted single crystal silicon layer is prone to generation of large number of defects especially at high carbon concentration. The present invention provides structures and methods for providing low defect carbon-substituted single crystal silicon layer even for high concentration of carbon in the silicon. According to the present invention, the active retrograde profile in the carbon implantation reduces the defect density in the carbon-substituted single crystal silicon layer obtained after a solid phase epitaxy. This enables the formation of semiconductor structures with compressive stress and low defect density. When applied to semiconductor transistors, the present invention enables N-type field effect transistors with enhanced electron mobility through the tensile stress that is present into the channel.

Abstract translation: 碳取代的单晶硅层的形成容易产生大量的缺陷，特别是在高碳浓度下。 本发明提供即使对于硅中的高浓度碳来提供低缺陷碳取代的单晶硅层的结构和方法。 根据本发明，碳注入中的主动逆行曲线减少了在固相外延后获得的碳取代单晶硅层中的缺陷密度。 这使得能够形成具有压缩应力和低缺陷密度的半导体结构。 当应用于半导体晶体管时，本发明能够通过存在于沟道中的拉伸应力使具有增强的电子迁移率的N型场效应晶体管成为可能。

公开(公告)号：US20070114605A1

公开(公告)日：2007-05-24

申请号：US11164376

申请日：2005-11-21

Applicant: Thomas Dyer ,  Jinghong Li ,  Zhijiong Luo

Inventor： Thomas Dyer ,  Jinghong Li ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/2658 ,  H01L21/28247

Abstract: A method of formation of integrated circuit devices includes forming a gate electrode stack over a portion of a semiconductor. The stack includes a gate dielectric layer with a gate electrode thereabove. Implant diatomic nitrogen and/or nitrogen atoms into the substrate aside from the stack at a maximum energy less than or equal to 10 keV for diatomic nitrogen and at a maximum energy less than or equal to 5 keV for atomic nitrogen at a temperature less than or equal to 1000° C. for a time of less than or equal to 30 minutes. Then form silicon oxide offset spacers on sidewalls of the stack. Form source/drain extension regions in the substrate aside from the offset spacers. Form nitride sidewall spacers on outer surfaces of the offset spacers over another portion of the nitrogen implanted layer. Then form source/drain regions in the substrate aside from the sidewall spacers.

Abstract translation: 形成集成电路器件的方法包括在半导体的一部分上形成栅电极堆叠。 堆叠包括其上方具有栅电极的栅介质层。 将双原子氮和/或氮原子从堆叠中以最低能量小于或等于10keV的双原子氮并且在小于或等于5keV的最大能量下，在低于或等于 等于1000℃，时间小于或等于30分钟。 然后在堆叠的侧壁上形成氧化硅偏移间隔物。 在偏移间隔物之外的衬底中形成源极/漏极延伸区域。 在氮注入层的另一部分上的偏移间隔物的外表面上形成氮化物侧壁间隔物。 然后在侧壁间隔物之外形成衬底中的源极/漏极区域。

公开(公告)号：US09105741B2

公开(公告)日：2015-08-11

申请号：US13614062

申请日：2012-09-13

Applicant: Kevin K. Chan ,  Jinghong Li ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Qingyun Yang

Inventor： Kevin K. Chan ,  Jinghong Li ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Qingyun Yang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/7848

Abstract: A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.

Abstract translation: 形成半导体结构的方法可以包括形成至少一个翅片并且在所述至少一个翅片结构的第一部分上形成栅极。 栅极间隔物可以形成在栅极的侧壁上，由此间隔物的形成产生与该至少一个鳍片的侧壁相邻的凹陷区域。 形成第一外延区域，其覆盖所述凹陷区域中的一个和所述至少一个翅片的第二部分，使得所述第二部分从所述栅极间隔物之一向外延伸。 通过蚀刻第一外延区域和至少一个鳍片的第二部分，在一个凹陷区域内形成第一外延层。 第二外延区域形成在相邻一个间隔物的位置和在一个凹陷区域内的第一外延层上方。

公开(公告)号：US20140070316A1

公开(公告)日：2014-03-13

申请号：US13614062

申请日：2012-09-13

Applicant: Kevin K. Chan ,  Jinghong Li ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Qingyun Yang

Inventor： Kevin K. Chan ,  Jinghong Li ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Qingyun Yang

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/7848

Abstract: A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.

Abstract translation: 形成半导体结构的方法可以包括形成至少一个翅片并且在所述至少一个翅片结构的第一部分上形成栅极。 栅极间隔物可以形成在栅极的侧壁上，由此间隔物的形成产生与该至少一个鳍片的侧壁相邻的凹陷区域。 形成第一外延区域，其覆盖所述凹陷区域中的一个和所述至少一个翅片的第二部分，使得所述第二部分从所述栅极间隔物之一向外延伸。 通过蚀刻第一外延区域和至少一个鳍片的第二部分，在一个凹陷区域内形成第一外延层。 第二外延区域形成在相邻一个间隔物的位置和在一个凹陷区域内的第一外延层上方。

公开(公告)号：US08299535B2

公开(公告)日：2012-10-30

申请号：US12823163

申请日：2010-06-25

Applicant: Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

Inventor： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括从底部到顶部的第一外延掺杂半导体材料的第一层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变;第二层 位于第一层顶部的第二外延掺杂半导体材料和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角形单层的上表面上的金属半导体合金触点。

公开(公告)号：US20120261717A1

公开(公告)日：2012-10-18

申请号：US13533499

申请日：2012-06-26

Applicant: Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

Inventor： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC: H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.

Abstract translation: 公开了包括位于半导体衬底上的至少一个FET栅叠层的半导体结构。 所述至少一个FET栅极堆叠包括位于半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 嵌入式应力元件位于至少一个FET栅极堆叠的相对侧并且位于半导体衬底内。 每个应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，以及第二外延掺杂半导体材料的上层。 至少一个单层的掺杂剂位于每个嵌入的应力元件的上层内。

公开(公告)号：US20120121251A1

公开(公告)日：2012-05-17

申请号：US13356712

申请日：2012-01-24

Applicant: Anthony J. Ticknor ,  Jinghong Li ,  Robert Lombaerde

Inventor： Anthony J. Ticknor ,  Jinghong Li ,  Robert Lombaerde

IPC: H04B10/08

CPC classification number: G05B23/0256

Abstract: A method, a system, and a computer program product for managing one or more electronic devices. Performance of an electronic device is monitored and presented to a user through a digital agent interface. The performance of the electronic device is controlled automatically by digital agent through the digital agent interface. The invention also enables automatic testing of the electronic device through the digital agent interface by setting up test configurations, activating test signals, and interpreting any error codes that may be generated.

Abstract translation: 一种用于管理一个或多个电子设备的方法，系统和计算机程序产品。 监视电子设备的性能并通过数字代理接口向用户呈现。 电子设备的性能由数字代理通过数字代理接口自动控制。 本发明还能够通过设置测试配置，激活测试信号和解释可能产生的任何错误代码，通过数字代理接口来自动测试电子设备。

公开(公告)号：US20110316044A1

公开(公告)日：2011-12-29

申请号：US12823163

申请日：2010-06-25

Applicant: Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

Inventor： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括从底部到顶部的第一外延掺杂半导体材料的第一层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变;第二层 位于第一层顶部的第二外延掺杂半导体材料和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角形单层的上表面上的金属半导体合金触点。

公开(公告)号：US08043920B2

公开(公告)日：2011-10-25

申请号：US12561606

申请日：2009-09-17

Applicant: Kevin K. Chan ,  Thomas Safron Kanarsky ,  Jinghong Li ,  Christine Qiqing Ouyang ,  Dae-Gyu Park ,  Zhibin Ren ,  Xinhui Wang ,  Haizhou Yin

Inventor： Kevin K. Chan ,  Thomas Safron Kanarsky ,  Jinghong Li ,  Christine Qiqing Ouyang ,  Dae-Gyu Park ,  Zhibin Ren ,  Xinhui Wang ,  Haizhou Yin

IPC: H01L21/00

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.

Abstract translation: 一种合并多鳍鳍鳍鳍片的制造方法和结构。 该方法包括从具有非常薄的掩埋氧化物层的SOI衬底的硅层形成单晶硅散热片，并通过从衬底生长垂直外延硅并从散热片的端部生成水平外延硅，从而将翅片的端部区域合并 垂直外延硅生长占优势。