公开(公告)号：US20100080076A1

公开(公告)日：2010-04-01

申请号：US12241192

申请日：2008-09-30

Applicant: Kuljit S. Bains ,  John Halbert

Inventor： Kuljit S. Bains ,  John Halbert

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C7/1021 ,  G11C7/1045 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/108

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a x4 mode, a x8 mode, and a x16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.

Abstract translation: 本发明的实施例通常涉及用于可变设备宽度和可缩放预取和页面大小的公共存储器设备的系统，方法和设备。 在一些实施例中，公共存储器件（例如DRAM）可以以包括例如x4模式，x8模式和x16模式在内的多种模式中的任何一种工作。 由DRAM提供的页面大小可以根据DRAM的模式而变化。 在一些实施例中，由DRAM预取的数据量也根据DRAM的模式而变化。

公开(公告)号：US07404055B2

公开(公告)日：2008-07-22

申请号：US11392471

申请日：2006-03-28

Applicant: Kuljit Bains ,  John Halbert ,  Greg Lemos ,  Randy Osborne

Inventor： Kuljit Bains ,  John Halbert ,  Greg Lemos ,  Randy Osborne

IPC: G06F12/00

CPC classification number: G06F13/1678

Abstract: In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a second format having a second width, where the critical portion is included in a first frame. The critical portion may include a cacheline mapped over a memory device rank. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，数据可以以具有第一宽度的第一格式从第一存储器传送到第二存储器代理，并且数据的至少关键部分可以从第二存储器代理返回到第一存储器 具有第二宽度的第二格式，其中临界部分包括在第一帧中。 关键部分可以包括在存储器设备等级上映射的高速缓存线。 描述和要求保护其他实施例。

公开(公告)号：US07349233B2

公开(公告)日：2008-03-25

申请号：US11388464

申请日：2006-03-24

Applicant: Kuljit S. Bains ,  John Halbert

Inventor： Kuljit S. Bains ,  John Halbert

IPC: G11C5/06 ,  G11C5/02 ,  G11C7/10

CPC classification number: G11C8/12

Abstract: In some embodiments, a chip includes at least four groups of memory banks and at least four groups of output conductors wherein each group of output conductors corresponds to a different one of the groups of memory banks. The chip also includes circuitry to perform a read operation by providing read data from at least one of the banks of each of the groups of memory banks to its corresponding group of output conductors. Other embodiments are described.

Abstract translation: 在一些实施例中，芯片包括至少四组存储器组和至少四组输出导体，其中每组输出导体对应于存储器组组中的不同组。 芯片还包括通过将存储器组中的每一组的至少一个存储体的读取数据提供给其对应的输出导体组来执行读取操作的电路。 描述其他实施例。

公开(公告)号：US07260007B2

公开(公告)日：2007-08-21

申请号：US11093905

申请日：2005-03-30

Applicant: Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

Inventor： Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

IPC: G11C5/06 ,  G11C7/04 ,  G11C7/00

CPC classification number: G11C5/04 ,  G01K7/425 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1063 ,  G11C11/40626 ,  G11C29/028 ,  G11C2029/5002

Abstract: Thermal management and communication is described in the context of memory modules that contain several memory devices. In one example, the invention includes determining a temperature of a first memory device, the first memory device containing a plurality of memory cells, determining a temperature of a second memory device after determining the temperature of the first memory device, the second memory device containing a plurality of memory cells, and generating an alarm based on an evaluation of the first and the second temperatures. In another example, the invention includes detecting a thermal event on a memory device of a memory module that contains a plurality of memory devices, detecting the state of an event bus of the memory module, and sending an alert on the event bus if the event bus is in an unoccupied state.

Abstract translation: 在包含多个存储器件的存储器模块的上下文中描述了热管理和通信。 在一个示例中，本发明包括确定第一存储器件的温度，第一存储器件包含多个存储器单元，在确定第一存储器件的温度之后确定第二存储器件的温度，第二存储器器件包含 多个存储单元，并且基于第一和第二温度的评估来产生报警。 在另一个示例中，本发明包括检测包含多个存储器件的存储器模块的存储器件上的热事件，检测存储器模块的事件总线的状态，以及如果事件发生在事件总线上的警报 公共汽车处于空闲状态。

公开(公告)号：US20070130374A1

公开(公告)日：2007-06-07

申请号：US11280837

申请日：2005-11-15

Applicant: Kuljit Bains ,  John Halbert ,  Randy Osborne

Inventor： Kuljit Bains ,  John Halbert ,  Randy Osborne

IPC: G06F3/00

CPC classification number: G06F13/1694

Abstract: In some embodiments, a chip includes memory banks and data ports, including at least first and second data ports, coupled to the memory banks. The chip also includes control circuitry to control a configuration of the first data port to be in one of multiple configurations in response to a configuration command, wherein the available configurations for the first data port include at least two of the following: whether the first data port (1) may only be used for read transactions, (2) may only be used for write transactions, or (3) may be used for either read or write transactions while in the configuration. Other embodiments are described.

Abstract translation: 在一些实施例中，芯片包括耦合到存储体的存储器组和数据端口，包括至少第一和第二数据端口。 该芯片还包括控制电路，用于响应于配置命令将第一数据端口的配置控制为多个配置之一，其中第一数据端口的可用配置包括以下中的至少两个：第一数据 端口（1）只能用于读取事务，（2）只能用于写入事务，或者（3）可以在配置中用于读取或写入事务。 描述其他实施例。

公开(公告)号：US20060236042A1

公开(公告)日：2006-10-19

申请号：US11096271

申请日：2005-03-31

Applicant: Sandeep Jain ,  John Halbert ,  Nilesh Shah

Inventor： Sandeep Jain ,  John Halbert ,  Nilesh Shah

IPC: G06F13/00

CPC classification number: G06F13/4239

Abstract: Data is transmitted from a memory device along with a training sequence to deswizzle the data. The training sequence may be sent, for example, when the memory device is initialized, or it may be appended to the data. A memory controller may include logic to receive the data and training sequence and deswizzle the data in response to the training sequence to identify the location of data on various signal lines. Other embodiments are described and claimed.

Abstract translation: 数据从存储器装置连同训练序列一起发送以去除数据。 训练序列可以例如在存储器件初始化时被发送，或者可以附加到数据。 存储器控制器可以包括用于接收数据和训练序列的逻辑，并且响应于训练序列去除数据以识别各种信号线上的数据的位置。 描述和要求保护其他实施例。

公开(公告)号：US20060221741A1

公开(公告)日：2006-10-05

申请号：US11093905

申请日：2005-03-30

Applicant: Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

Inventor： Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

IPC: G11C7/04

CPC classification number: G11C5/04 ,  G01K7/425 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1063 ,  G11C11/40626 ,  G11C29/028 ,  G11C2029/5002

Abstract: Thermal management and communication is described in the context of memory modules that contain several memory devices. In one example, the invention includes determining a temperature of a first memory device, the first memory device containing a plurality of memory cells, determining a temperature of a second memory device after determining the temperature of the first memory device, the second memory device containing a plurality of memory cells, and generating an alarm based on an evaluation of the first and the second temperatures. In another example, the invention includes detecting a thermal event on a memory device of a memory module that contains a plurality of memory devices, detecting the state of an event bus of the memory module, and sending an alert on the event bus if the event bus is in an unoccupied state.

Abstract translation: 在包含多个存储器件的存储器模块的上下文中描述了热管理和通信。 在一个示例中，本发明包括确定第一存储器件的温度，第一存储器件包含多个存储器单元，在确定第一存储器件的温度之后确定第二存储器件的温度，第二存储器器件包含 多个存储单元，并且基于第一和第二温度的评估来产生报警。 在另一个示例中，本发明包括检测包含多个存储器件的存储器模块的存储器件上的热事件，检测存储器模块的事件总线的状态，以及如果事件发生在事件总线上的警报 公共汽车处于空闲状态。

公开(公告)号：US20050259480A1

公开(公告)日：2005-11-24

申请号：US11192249

申请日：2005-07-27

Applicant: Kuljit Bains ,  Robert Ellis ,  Chris Freeman ,  John Halbert ,  David Zimmerman

Inventor： Kuljit Bains ,  Robert Ellis ,  Chris Freeman ,  John Halbert ,  David Zimmerman

IPC: G11C5/00 ,  G11C29/48 ,  G11C29/56

CPC classification number: G11C29/48 ,  G11C29/56 ,  G11C2029/5602

Abstract: Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.

Abstract translation: 本发明的一些实施例使得驻留在存储器模块上的存储器设备的调试功能能够通过缓冲器芯片从存储器总线缓冲。 一些实施例将来自耦合到缓冲器芯片和存储器总线之间的高速接口的测试仪的连接器信号映射到缓冲器芯片和存储器件之间的接口。 在测试模式期间，一些实施例绕过缓冲芯片的正常操作电路并提供与存储器件的直接连接。 其他实施例使用缓冲芯片的现有架构将高速引脚转换成低速引脚并将其映射到连接到存储器件的引脚。 在权利要求中描述了其它实施例。

公开(公告)号：US06369605B1

公开(公告)日：2002-04-09

申请号：US09664994

申请日：2000-09-18

Applicant: Randy Bonella ,  John Halbert

Inventor： Randy Bonella ,  John Halbert

IPC: H03K1716

CPC classification number: H03K19/018585

Abstract: An output driver circuit within an electronic device to provide a configurable driver circuit. When placed in a first mode of operation, the driver circuit drives an output signal. When placed in a second mode of operation, the driver circuit provides impedance matching to prevent signal reflection.

Abstract translation: 电子设备内的输出驱动器电路，用于提供可配置的驱动电路。 当处于第一操作模式时，驱动器电路驱动输出信号。 当处于第二操作模式时，驱动电路提供阻抗匹配以防止信号反射。

公开(公告)号：US08238189B2

公开(公告)日：2012-08-07

申请号：US13096137

申请日：2011-04-28

Applicant: Kuljit S. Bains ,  John Halbert

Inventor： Kuljit S. Bains ,  John Halbert

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C7/1021 ,  G11C7/1045 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/108

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a ×4 mode, a ×8 mode, and a ×16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.

Abstract translation: 本发明的实施例通常涉及用于可变设备宽度和可缩放预取和页面大小的公共存储器设备的系统，方法和设备。 在一些实施例中，公共存储器件（例如DRAM）可以以包括例如×4模式，×8模式和×16模式在内的多种模式中的任何一种工作。 由DRAM提供的页面大小可以根据DRAM的模式而变化。 在一些实施例中，由DRAM预取的数据量也根据DRAM的模式而变化。