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    Dynamic core swapping
    3.
    发明授权
    Dynamic core swapping 有权

    公开(公告)号：US08156351B2

    公开(公告)日：2012-04-10

    申请号：US12326775

    申请日：2008-12-02

    申请人： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

    发明人： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

    IPC分类号： G06F1/00 ,  G06F1/32

    摘要： An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

    Various Methods and Apparatuses for Power States in a Controller
    4.
    发明申请
    Various Methods and Apparatuses for Power States in a Controller 审中-公开
    控制器中功率状态的各种方法和装置

    公开(公告)号：US20100083013A1

    公开(公告)日：2010-04-01

    申请号：US12632548

    申请日：2009-12-07

    申请人： James P. Kardach ,  Barnes Cooper ,  Seh Kwa ,  Animesh Mishra ,  Paul Diefenbaugh

    发明人： James P. Kardach ,  Barnes Cooper ,  Seh Kwa ,  Animesh Mishra ,  Paul Diefenbaugh

    IPC分类号： G06F1/00 ,  G06F1/32

    CPC分类号： G06F1/3203 ,  G06F1/325

    摘要： Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event.

    摘要翻译： 描述了各种方法，装置和系统，其中芯片组控制器具有控制与计算设备中的外围设备的通信的电路。 芯片组控制器具有逻辑配置1）当外围设备连接到芯片组控制器时检测插件事件，以及2）基于逻辑检测来将芯片组控制器从低功耗状态转换到更高功耗状态 插件事件。

    THROTTLING MEMORY IN A COMPUTER SYSTEM
    5.
    发明申请
    THROTTLING MEMORY IN A COMPUTER SYSTEM 审中-公开
    计算机系统中的重力记忆

    公开(公告)号：US20090262783A1

    公开(公告)日：2009-10-22

    申请号：US12495510

    申请日：2009-06-30

    申请人： Pochang Hsu ,  Animesh Mishra ,  Jun Shi

    发明人： Pochang Hsu ,  Animesh Mishra ,  Jun Shi

    IPC分类号： G01K13/00

    CPC分类号： G01K13/00 ,  G06F1/206 ,  G06F1/3203 ,  G06F13/16 ,  G11C5/04 ,  G11C5/143 ,  G11C7/04 ,  Y02D10/16

    摘要： Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one embodiment a memory unit includes a memory device and a temperature measurement module coupled to the memory device. The temperature measurement device measures the internal temperature of the memory device. Memory throttling can therefore be implemented based on more accurate measurements and with a much shorter response time.

    摘要翻译： 管理存储器件的系统和方法通过增强的存储器节流来提供降低的功耗和更好的热管理。 在一个实施例中，存储器单元包括耦合到存储器件的存储器件和温度测量模块。 温度测量装置测量存储器件的内部温度。 因此，可以基于更准确的测量并且具有短得多的响应时间来实现内存限制。

    DYNAMIC CORE SWAPPING
    6.
    发明申请
    DYNAMIC CORE SWAPPING 有权
    动态核心切换

    公开(公告)号：US20090083554A1

    公开(公告)日：2009-03-26

    申请号：US12326775

    申请日：2008-12-02

    申请人： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

    发明人： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

    IPC分类号： G06F1/26 ,  G06F12/08 ,  G06F1/32

    CPC分类号： G06F9/4418 ,  G06F1/3228 ,  G06F1/3275 ,  G06F1/3293 ,  G06F9/3867 ,  G06F9/4401 ,  G06F12/0842 ,  G06F13/4282 ,  G06F15/80 ,  Y02D10/151

    摘要： An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

    摘要翻译： 本发明的实施例是用于动态地交换处理器核心的技术。 第一个核心有一个第一个指令集。 第一个核心以第一个性能级别执行程序。 当触发事件发生时，第一个内核停止执行程序。 第二核心具有与第一指令集兼容的第二指令集，并且具有与第一性能级别不同的第二性能级别。 当第一个核心执行程序时，第二个内核处于掉电状态。 在第一核心停止执行程序之后，电路对第二核心供电，使得第二核心继续在第二性能级别执行程序。

    THROTTLING MEMORY IN A COMPUTER SYSTEM
    7.
    发明申请
    THROTTLING MEMORY IN A COMPUTER SYSTEM 有权
    计算机系统中的重力记忆

    公开(公告)号：US20080043808A1

    公开(公告)日：2008-02-21

    申请号：US11924754

    申请日：2007-10-26

    申请人： Pochang Hsu ,  Animesh Mishra ,  Jun Shi

    发明人： Pochang Hsu ,  Animesh Mishra ,  Jun Shi

    IPC分类号： G01K1/02 ,  G06F12/00

    CPC分类号： G01K13/00 ,  G06F1/206 ,  G06F1/3203 ,  G06F13/16 ,  G11C5/04 ,  G11C5/143 ,  G11C7/04 ,  Y02D10/16

    摘要： Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one embodiment a memory unit includes a memory device and a temperature measurement module coupled to the memory device. The temperature measurement device measures the internal temperature of the memory device. Memory throttling can therefore be implemented based on more accurate measurements and with a much shorter response time.

    摘要翻译： 管理存储器件的系统和方法通过增强的存储器节流来提供降低的功耗和更好的热管理。 在一个实施例中，存储器单元包括耦合到存储器件的存储器件和温度测量模块。 温度测量装置测量存储器件的内部温度。 因此，可以基于更准确的测量并且具有短得多的响应时间来实现内存限制。

    Dynamic lane, voltage and frequency adjustment for serial interconnect
    8.
    发明授权
    Dynamic lane, voltage and frequency adjustment for serial interconnect 有权
    串行互连的动态通道，电压和频率调整

    公开(公告)号：US07197591B2

    公开(公告)日：2007-03-27

    申请号：US10882544

    申请日：2004-06-30

    申请人： Seh Kwa ,  Animesh Mishra

    发明人： Seh Kwa ,  Animesh Mishra

    IPC分类号： G06F1/26 ,  G06F13/00 ,  G06F13/14 ,  H03K19/0175 ,  G09G3/00

    CPC分类号： G06F13/4072 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/172

    摘要： A method is described which comprises propagating electronic signals within circuitry comprising a transmitter to select a number of the transmitter's lanes, set a speed for each of the lanes, and set at least a driver supply voltage for each of the lanes. The number and speed determine the transmitter's bandwidth. Power consumed by the transmitter as a consequence of the lane number selection, lane speed setting and driver supply voltage is less than a power that would have been consumed by the transmitter had another available combination of lane number, lane speed and supply voltage been effected for the transmitter.

    摘要翻译： 描述了一种方法，其包括在包括发射器的电路内传播电子信号，以选择多个发射机的通道，为每个通道设置速度，并且至少为每个车道设置驱动器电源电压。 数量和速度决定了发射机的带宽。 作为通道号选择，通道速度设置和驱动器电源电压的结果，由发射机消耗的功率小于发射机已消耗的功率，具有车道号，车道速度和电源电压的另一种可用组合， 发射机。

    Method, apparatus, and system for active refresh management
    10.
    发明申请
    Method, apparatus, and system for active refresh management 有权
    用于主动刷新管理的方法，装置和系统

    公开(公告)号：US20060133173A1

    公开(公告)日：2006-06-22

    申请号：US11019881

    申请日：2004-12-21

    申请人： Sandeep Jain ,  Animesh Mishra ,  John Halbert

    发明人： Sandeep Jain ,  Animesh Mishra ,  John Halbert

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40611 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622

    摘要： A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.

    摘要翻译： 一种能够实现DRAM的部分刷新方案的方法，装置和系统，其包括至少指定刷新开始值或刷新开始值和刷新结束值，以减少刷新周期期间必须刷新的行数 ，从而减少刷新期间消耗的功率量。