公开(公告)号：US20100302884A1

公开(公告)日：2010-12-02

申请号：US12662247

申请日：2010-04-07

Applicant: Kwang-Jin Lee ,  Yong-Jun Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Joon-Yong Choi

Inventor： Kwang-Jin Lee ,  Yong-Jun Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Joon-Yong Choi

IPC: G11C7/00

CPC classification number: G11C7/04 ,  G11C7/18 ,  G11C7/22 ,  G11C16/32 ,  G11C2207/002

Abstract: Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.

Abstract translation: 公开了一种防止用于非易失性半导体存储器件的耦合噪声的方法。 根据该方法，如果写入操作信号的边缘与读取操作信号的激活时段重叠，则产生检查结果。 基于检查结果修改写操作信号。

公开(公告)号：US20100284221A1

公开(公告)日：2010-11-11

申请号：US12659690

申请日：2010-03-17

Applicant: Joon-Yong Choi ,  Byunggil Choi ,  Yu Hwan Ro ,  Yong-Jun Lee

Inventor： Joon-Yong Choi ,  Byunggil Choi ,  Yu Hwan Ro ,  Yong-Jun Lee

IPC: G11C16/04

CPC classification number: G11C16/08

Abstract: A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.

Abstract translation: 非易失性存储器件包括全局选择线，局部选择线，第一选择电路和第二选择电路。 本地线分别对应于全局选择线。 第一选择电路被配置为连接到全局选择线以选择全局选择线。 第二选择电路连接在全局选择线和本地选择线之间，并被配置为选择本地选择线。 第一选择电路被配置为选择至少一个全局选择线，并且第二选择电路被配置为在连续激活至少一个全局选择线的同时选择与所选择的全局选择线对应的本地选择线。

公开(公告)号：US20100103725A1

公开(公告)日：2010-04-29

申请号：US12574227

申请日：2009-10-06

Applicant: HoJung Kim ,  Joon-Yong Choi

Inventor： HoJung Kim ,  Joon-Yong Choi

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/004 ,  G11C7/02 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2013/0054 ,  G11C2213/72

Abstract: The present invention relates to a resistance variable memory device, and more particularly, to a resistance variable memory device capable of preventing an effect of coupling noise. The resistance variable memory device includes: a memory cell connected to a bit line; a precharge circuit precharging the bit line in response to a precharge signal; a bias circuit providing a bias voltage to the bit line in response to,a bias signal; and a control logic controlling the precharge signal and the bias signal. The control logic provides the bias signal to the bias circuit at a precharge interval. Accordingly, the resistance variable memory device according to the present invention can prevent an effect coupling noise.

Abstract translation: 电阻变化存储装置技术领域本发明涉及一种电阻可变存储装置，更具体地，涉及一种能够防止耦合噪声影响的电阻变化存储装置。 电阻变化存储装置包括：连接到位线的存储单元; 预充电电路响应于预充电信号预充电所述位线; 偏置电路，响应于偏置信号向位线提供偏置电压; 以及控制逻辑来控制预充电信号和偏置信号。 控制逻辑以预充电间隔将偏置信号提供给偏置电路。 因此，根据本发明的电阻变化存储装置可以防止耦合噪声的影响。

公开(公告)号：US20080112220A1

公开(公告)日：2008-05-15

申请号：US11984145

申请日：2007-11-14

Applicant: Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

Inventor： Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C7/225 ,  G11C16/10

Abstract: A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.

Abstract translation: 非易失性半导体存储器件可以包括可以包括多个存储晶体管的存储单元阵列; 输入电路，其可以响应于MRS修剪代码或电熔丝修剪代码来控制内部参考电压的电压电平和内部时钟信号的延迟时间，并且可以产生第一缓冲输入信号; 列门，其可以响应于解码列地址信号而选通第一缓冲输入信号; 以及读出放大器，其可以放大存储单元阵列的输出信号以输出到列门，并且可以接收列门的输出信号以输出到存储器单元阵列。 非易失性半导体存储器件可以适当地缓冲小摆动范围的输入信号。