公开(公告)号：US06305095B1

公开(公告)日：2001-10-23

申请号：US09513885

申请日：2000-02-25

Applicant: Kevin T. Look ,  Shih-Cheng Hsueh

Inventor： Kevin T. Look ,  Shih-Cheng Hsueh

IPC: G01B700

CPC classification number: G03F7/70633 ,  G01B7/003 ,  H01L22/34

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

Abstract translation: 描述了掩模对准检测结构，其测量使用电阻元件的集成电路的层之间的未对准的方向和程度，其中电阻随着一维中的未对准而变化。 根据本发明的测量对于工艺变化相对不敏感，并且用于进行这些测量的结构可以与使用标准工艺的集成电路上的其它特征一起形成。 本发明的一个实施例可用于测量两个导电层之间的未对准。 其他实施例测量扩散区域和导体之间以及扩散区域和窗口之间的未对准，通过该窗口将形成其他扩散区域。 根据一个实施例的电路包括行和列解码器，用于独立地选择掩模对准检测结构以减少实现检测结构所需的测试终端的数量。

公开(公告)号：US6057589A

公开(公告)日：2000-05-02

申请号：US61817

申请日：1998-04-16

Applicant: Kevin T. Look ,  Yakov Karpovich ,  Michael J. Hart

Inventor： Kevin T. Look ,  Yakov Karpovich ,  Michael J. Hart

IPC: H01L23/525 ,  H01L29/00 ,  H01L21/70

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: An over-etched (OE) antifuse includes a lower electrode, an antifuse layer contacting the lower electrode by an over-etched via, and a second conductive layer formed on the antifuse layer. This over-etched via forms a trench in the lower electrode, wherein in one embodiment the depth of the trench approximates the thickness of the antifuse layer. The trench narrows the programming voltage distribution of the antifuses on the device, irrespective of topology. Because active circuits can be placed underneath the OE antifuses, the present invention dramatically reduces chip size in comparison to conventional devices.

Abstract translation: 过蚀刻（OE）反熔丝包括下电极，通过过蚀刻通孔与下电极接触的反熔丝层，以及形成在反熔丝层上的第二导电层。 该过蚀刻通孔在下电极中形成沟槽，其中在一个实施例中，沟槽的深度接近反熔丝层的厚度。 沟槽缩小了设备上反熔文件的编程电压分布，而不考虑拓扑结构。 由于有源电路可以放置在OE反熔丝之下，因此与传统的器件相比，本发明显着地减小了芯片的尺寸。

公开(公告)号：US5970372A

公开(公告)日：1999-10-19

申请号：US1022

申请日：1997-12-30

Applicant: Michael J. Hart ,  Kevin T. Look ,  Yakov Karpovich

Inventor： Michael J. Hart ,  Kevin T. Look ,  Yakov Karpovich

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic devices are also provided which include the antifuses.

Abstract translation: 提供了包括第一和第二导电层以及位于第一和第二导电层之间的反熔丝层的防潮装置。 反熔丝层包括位于两个非晶硅层之间的至少一个氧化物层。 还提供了互连结构和可编程逻辑器件，其包括反熔丝。

公开(公告)号：US09041409B1

公开(公告)日：2015-05-26

申请号：US13348549

申请日：2012-01-11

Applicant: Kevin T. Look

Inventor： Kevin T. Look

IPC: G01R31/08 ,  G01R31/26 ,  G01R31/28

CPC classification number: G01R31/08 ,  G01R31/026 ,  G01R31/2812 ,  G01R31/2851 ,  G01R31/2889

Abstract: An integrated circuit structure can include a plurality of solder bumps coupled in series forming a chain and a plurality of diodes, wherein each diode is coupled to one of the plurality of solder bumps. The integrated circuit structure also can include a first pad coupled to the solder bump of the plurality of solder bumps at an end of the chain. The first pad can be configured to provide a test current responsive to application of a forward bias voltage to each diode of the plurality of diodes.

Abstract translation: 集成电路结构可以包括串联连接形成链和多个二极管的多个焊料凸块，其中每个二极管耦合到多个焊料凸块中的一个。 集成电路结构还可以包括在链的端部处耦合到多个焊料凸块的焊料凸块的第一焊盘。 可以将第一焊盘配置成响应于向多个二极管中的每个二极管施加正向偏置电压而提供测试电流。

公开(公告)号：US06671205B2

公开(公告)日：2003-12-30

申请号：US10283736

申请日：2002-10-29

Applicant: Kevin T. Look

Inventor： Kevin T. Look

IPC: G11C700

CPC classification number: H01L29/66825 ,  G11C16/0408 ,  H01L23/345 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a programming voltage is applied across the metal silicide layer, there is intense localized heating. The heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. The heating causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device.

公开(公告)号：US06436726B1

公开(公告)日：2002-08-20

申请号：US09906286

申请日：2001-07-16

Applicant: Kevin T. Look ,  Shih-Cheng Hsueh

Inventor： Kevin T. Look ,  Shih-Cheng Hsueh

IPC: G01R3126

Abstract: Mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

公开(公告)号：US06393714B1

公开(公告)日：2002-05-28

申请号：US09512779

申请日：2000-02-25

Applicant: Kevin T. Look ,  Shih-Cheng Hsueh

Inventor： Kevin T. Look ,  Shih-Cheng Hsueh

IPC: G01D2100

CPC classification number: G03F7/70633 ,  G03F7/70658 ,  H01L22/34

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

Abstract translation: 描述了掩模对准检测结构，其测量使用电阻元件的集成电路的层之间的未对准的方向和程度，其中电阻随着一维中的未对准而变化。 根据本发明的测量对于工艺变化相对不敏感，并且用于进行这些测量的结构可以与使用标准工艺的集成电路上的其它特征一起形成。 本发明的一个实施例可用于测量两个导电层之间的未对准。 其他实施例测量扩散区域和导体之间以及扩散区域和窗口之间的未对准，通过该窗口将形成其他扩散区域。 根据一个实施例的电路包括行和列解码器，用于独立地选择掩模对准检测结构以减少实现检测结构所需的测试终端的数量。

公开(公告)号：US5786240A

公开(公告)日：1998-07-28

申请号：US672185

申请日：1996-06-27

Applicant: Kevin T. Look ,  Yakov Karpovich ,  Michael J. Hart

Inventor： Kevin T. Look ,  Yakov Karpovich ,  Michael J. Hart

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S148/055

Abstract: An over-etched (OE) antifuse includes a lower electrode, an antifuse layer contacting the lower electrode by an over-etched via, and a second conductive layer formed on the antifuse layer. This over-etched via forms a trench in the lower electrode, wherein in one embodiment the depth of the trench approximates the thickness of the antifuse layer. The trench narrows the programming voltage distribution of the antifuses on the device, irrespective of topology. Because active circuits can be placed underneath the OE antifuses, the present invention dramatically reduces chip size in comparison to conventional devices.

公开(公告)号：US5502000A

公开(公告)日：1996-03-26

申请号：US436995

申请日：1995-05-08

Applicant: Kevin T. Look ,  Evert A. Wolsheimer

Inventor： Kevin T. Look ,  Evert A. Wolsheimer

IPC: H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01L27/10 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

Abstract: An antifuse is provided which includes a first conductive layer, an antifuse layer formed on the first conductive layer, and a second conductive layer formed on the antifuse layer. A portion of the antifuse layer forms a substantially orthogonal angle with the first conductive layer and the second conductive layer. This "corner" formation of the antifuse enhances the electric field at this location during programming, thereby providing a predictable location for the filament, i.e. the conductive path between the first and second conductive layers. This antifuse provides other advantages including: a relatively low programming voltage, good step coverage for the antifuse layer and the upper conductive layer, a low, stable resistance value, and minimal shearing effects on the filament.

Abstract translation: 提供一种反熔丝，其包括第一导电层，形成在第一导电层上的反熔丝层，以及形成在反熔丝层上的第二导电层。 反熔丝层的一部分与第一导电层和第二导电层形成大致正交的角度。 反熔丝的这种“角”形成在编程期间增强了该位置处的电场，从而为灯丝提供可预测的位置，即第一和第二导电层之间的导电路径。 该反熔丝提供了其它优点，包括：相对较低的编程电压，反熔丝层和上导电层的良好阶梯覆盖，低稳定的电阻值以及对细丝的最小剪切效应。

公开(公告)号：US5486707A

公开(公告)日：1996-01-23

申请号：US182519

申请日：1994-01-10

Applicant: Kevin T. Look ,  Evert A. Wolsheimer

Inventor： Kevin T. Look ,  Evert A. Wolsheimer

IPC: H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01L27/10 ,  H01L29/04 ,  H01L27/02

CPC classification number: H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002

Abstract: An antifuse for programmable integrated circuit devices is formed above a refractory metal on a thin native oxide layer and comprises an amorphous compound resulting from an PECVD deposition using a combination of silane gas and nitrogen. After formation of the amorphous antifuse layer, the layer is implanted with an atomic species such as argon. The thin oxide layer is formed on the surface of a refractory metal, therefore the process of forming the oxide is slow, the oxide is of even thickness, and the thickness can be controlled precisely. In a preferred embodiment, a second thin oxide layer is formed above the doped amorphous layer. The oxide layers significantly reduce the leakage current of an unprogrammed antifuse. Because of these thin oxide layers and the implantation step, the amorphous layer may be as thin as 200 .ANG..

Abstract translation: 可编程集成电路器件的反熔丝形成在薄的自然氧化物层上的难熔金属上方，并且包括由使用硅烷气体和氮气的组合的PECVD沉积产生的无定形化合物。 在形成无定形反熔丝层之后，用诸如氩的原子物质注入该层。 在难熔金属的表面上形成薄的氧化物层，因此形成氧化物的过程缓慢，氧化物厚度均匀，可以精确地控制厚度。 在优选实施例中，在掺杂非晶层之上形成第二薄氧化物层。 氧化物层显着降低未编程的反熔丝的漏电流。 由于这些薄氧化物层和注入步骤，非晶层可以薄至200。