公开(公告)号：US20050153217A1

公开(公告)日：2005-07-14

申请号：US11012494

申请日：2004-12-16

申请人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/20 ,  G03F9/00 ,  G06F17/50 ,  H01L21/027

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： A pattern verification method comprising preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges, the positional displacement being displacement between first point and the evaluation point, computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.

摘要翻译： 一种图案验证方法，包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个工艺参数以计算所转印/形成的图案，定义 对于每个过程参数的参考值和可变范围，计算与评估点相对应的每个第一点的位置位移，使用校正掩模图案计算的第一点和通过改变其中的处理参数而获得的参数值的多个组合 可变范围或在各个可变范围内，位置偏移是第一点和评估点之间的位移，计算每个评估点的位置偏移的统计，以及根据统计信息输出修改掩模图案的信息。

公开(公告)号：US08490031B2

公开(公告)日：2013-07-16

申请号：US12771645

申请日：2010-04-30

申请人： Kyoko Izuha ,  Shunichi Shibuki ,  Takashi Sakairi

发明人： Kyoko Izuha ,  Shunichi Shibuki ,  Takashi Sakairi

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/12 ,  H01L21/31053 ,  H01L21/3212 ,  Y02P90/265

摘要： A method for manufacturing a semiconductor device includes the steps of reading physical layout data of a circuit to be manufactured and performing calculation to modify a pattern width in the physical layout data by a predetermined amount; reading a physical layout and analyzing a pattern that is predicted to remain as a step difference of a predetermined amount or more in a case where a planarization process is performed on a planarizing film on a pattern by a quantitative calculation by using at least one of a density of patterns, a pattern width, and a peripheral length of a range of interest and a range in the vicinity of the range of interest; and reading data of the pattern that is predicted to remain as a step difference, and making a correction to a layout in which a step difference of a predetermined amount or more does not remain.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：读取要制造的电路的物理布局数据，并执行计算以将物理布局数据中的图案宽度修改预定量; 在通过定量计算对图案上的平坦化膜进行平坦化处理的情况下，读取物理布局并分析预测将保持为预定量以上的阶差的图案，其中， 图案的密度，图案宽度和感兴趣范围的周边长度以及感兴趣的范围附近的范围; 并且读取预测为保持为步进差的图案的数据，并且对不会保留预定量以上的阶差的布局进行校正。

公开(公告)号：US08112724B2

公开(公告)日：2012-02-07

申请号：US12048532

申请日：2008-03-14

申请人： Kyoko Izuha

发明人： Kyoko Izuha

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A method of designing a semiconductor integrated circuit includes a cell arranging and wiring step of arranging and wiring cells for creating a physical layout, a design-rule checking step of verifying a shape of a second physical layout including the cells of the physical layout with reference to a rule library for design rule check, a mask-data creating step of creating mask data corresponding to the physical layout using the second physical layout when the design rule is satisfied in the design-rule checking step, a mask-data processing step of performing, when the design rule is not satisfied in the design-rule checking step, mask data processing for the verification-object second physical layout, and a mask-data creating step for creating mask data corresponding to the physical layout using the second physical layout subjected to the mask data processing in the mask-data processing data.

摘要翻译： 一种设计半导体集成电路的方法包括：布置和布线用于创建物理布局的单元的单元布置和布线步骤;设计规则检查步骤，用于参考来验证包括物理布局的单元格的第二物理布局的形状 涉及用于设计规则检查的规则库，掩模数据创建步骤，当在设计规则检查步骤中满足设计规则时，使用第二物理布局创建与物理布局相对应的掩模数据;掩模数据处理步骤 当在设计规则检查步骤中不满足设计规则时，执行用于验证对象第二物理布局的掩模数据处理以及掩模数据创建步骤，用于使用第二物理布局来创建对应于物理布局的掩模数据 在掩模数据处理数据中进行掩模数据处理。

公开(公告)号：US20110302543A1

公开(公告)日：2011-12-08

申请号：US13213714

申请日：2011-08-19

申请人： Kyoko Izuha

发明人： Kyoko Izuha

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A pattern designing method, including the steps of carrying out transfer simulation calculation and step simulation calculation by using physical layout data produced from circuit design data, and comparing a result of the transfer simulation calculation and the step simulation calculation with a preset standard; and carrying out calculation for electrical characteristics by using parameters obtained from the physical layout when as a result of the comparison, the preset standard is fulfilled, and carrying out calculation for the electrical characteristics by reflecting the result of the transfer simulation calculation and the step simulation calculation in the parameters when as the result of the comparison, the preset standard is not fulfilled, thereby extracting the parameters.

摘要翻译： 一种模式设计方法，包括通过使用从电路设计数据产生的物理布局数据进行传输仿真计算和步进模拟计算的步骤，并将传输模拟计算和步进模拟计算的结果与预设标准进行比较; 通过使用从物理布局获得的参数进行电特性的计算，作为比较的结果，满足预设标准，并通过反映传递模拟计算和步进模拟的结果来执行电特性的计算 在参数计算中作为比较结果，不能满足预设标准，从而提取参数。

公开(公告)号：US07631287B2

公开(公告)日：2009-12-08

申请号：US11727288

申请日：2007-03-26

申请人： Kyoko Izuha ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G03F7/705

摘要： A method in which a desired pattern is compared with a finish pattern to be formed on a wafer, which is predicted from a design pattern, based on a calculation of a light beam intensity, and a deviation quantity of the finish pattern from the desired pattern at each edge of the finish pattern and the desired pattern is calculated, comprising setting a reference light beam intensity for setting the desired pattern on a wafer, setting an evaluation point for comparison of the finish pattern with the desired pattern, calculating a light beam intensity at the evaluation point, calculating a differentiation value of the light beam intensity at the evaluation point, calculating an intersection of the differentiation value with the reference light beam intensity, and calculating a difference between the intersection and the evaluation point, the difference defining an edge deviation quantity of the finish pattern from the desired pattern.

摘要翻译： 将期望图案与根据设计图案预测的要在晶片上形成的光洁度图案进行比较的方法，基于光束强度的计算和完成图案与期望图案的偏差量 在完成图案的每个边缘处并计算所需图案，包括设置用于在晶片上设置期望图案的参考光束强度，设置用于将完成图案与期望图案进行比较的评估点，计算光束强度 在评价点，计算评价点的光束强度的微分值，计算微分值与参考光束强度的交点，计算交点与评价点之间的差，限定边缘的差 完成图案与期望图案的偏差量。

公开(公告)号：US07571417B2

公开(公告)日：2009-08-04

申请号：US11012494

申请日：2004-12-16

申请人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： A pattern verification method includes preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, and computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges. The positional displacement is a displacement between first point and the evaluation point. The method further includes computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.

摘要翻译： 模式验证方法包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个过程参数以计算所转移/形成的图案，定义 针对每个处理参数的参考值和可变范围，并且计算与评估点相对应的每个第一点的位置偏移，使用校正掩模图案计算的第一点和通过改变处理参数获得的参数值的多个组合 在可变范围内或在相应的可变范围内。 位置偏移是第一点与评价点之间的位移。 该方法还包括计算每个评估点的位置偏移的统计量，并根据统计信息输出修改掩模图案的信息。

公开(公告)号：US07541136B2

公开(公告)日：2009-06-02

申请号：US11472452

申请日：2006-06-22

申请人： Kyoko Izuha ,  Hideki Kanai ,  Soichi Inoue ,  Shingo Kanamitsu ,  Shinichi Ito

发明人： Kyoko Izuha ,  Hideki Kanai ,  Soichi Inoue ,  Shingo Kanamitsu ,  Shinichi Ito

IPC分类号： G03C5/00

CPC分类号： G03F1/30 ,  G03F1/32 ,  G03F7/70641 ,  G03F7/70683

摘要： Disclosed is a mask comprising a first area including a first surrounding area in which a halftone phase shift film or a stacked film of a halftone phase shift film and an opaque film is provided on a transparent substrate, and a first opening area surrounded by the first surrounding area, and a second area including a second surrounding area in which a halftone phase shift film is provided on the transparent substrate and a second opening area surrounded by the second surrounding area, wherein a transparent film is provided in at least a part of the second opening area, the transparent film being configured to give a predetermined phase difference to exposure light passing through that part of the second opening area in which the transparent film is provided relative to exposure light passing through the second surrounding area.

摘要翻译： 公开了一种掩模，其包括：第一区域，包括第一周围区域，在透明基板上设置有半色调相移膜或半色调相移膜的叠层膜和不透明膜;以及第一开口区域， 以及第二区域，其包括在透明基板上设置半色调相移膜的第二周围区域和由第二周围区域围绕的第二开口区域，其中在至少一部分中设置透明膜 第二开口区域，所述透明膜被配置为相对于穿过所述第二周围区域的曝光光而通过其中设置有所述透明膜的所述第二开口区域的那部分的曝光而给予预定的相位差。

公开(公告)号：US20070226676A1

公开(公告)日：2007-09-27

申请号：US11727288

申请日：2007-03-26

申请人： Kyoko Izuha ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G03F7/705

摘要： A method in which a desired pattern is compared with a finish pattern to be formed on a wafer, which is predicted from a design pattern, based on a calculation of a light beam intensity, and a deviation quantity of the finish pattern from the desired pattern at each edge of the finish pattern and the desired pattern is calculated, comprising setting a reference light beam intensity for setting the desired pattern on a wafer, setting an evaluation point for comparison of the finish pattern with the desired pattern, calculating a light beam intensity at the evaluation point, calculating a differentiation value of the light beam intensity at the evaluation point, calculating an intersection of the differentiation value with the reference light beam intensity, and calculating a difference between the intersection and the evaluation point, the difference defining an edge deviation quantity of the finish pattern from the desired pattern.

公开(公告)号：US07250235B2

公开(公告)日：2007-07-31

申请号：US10784277

申请日：2004-02-24

申请人： Kyoko Izuha ,  Masafumi Asano ,  Tadahito Fujisawa

发明人： Kyoko Izuha ,  Masafumi Asano ,  Tadahito Fujisawa

IPC分类号： G03F9/00 ,  G03C5/00

CPC分类号： G03F7/70641 ,  G03F1/44

摘要： A focus monitor method comprising preparing a mask comprising a first and second focus monitor patterns and an exposure monitor pattern, the focus monitor patterns being used to form first and second focus monitor marks on a wafer, and the exposure monitor pattern being used to form exposure meters on the wafer, obtaining a exposure dependency of a relationship between a dimensions of the focus monitor marks and the defocus amount, forming the focus monitor marks and exposure monitor mark on the wafer, measuring a dimension of the exposure monitor mark to obtain an effective exposure, selecting a relationship between the dimensions of the focus monitor marks and the defocus amount corresponding to the effective exposure, measuring a dimensions of the first and second focus monitor marks, and obtaining a defocus amount in accordance with the measured dimensions of the focus monitor marks and the selected relationship.

摘要翻译： 一种聚焦监视器方法，包括准备包括第一和第二聚焦监视器图案和曝光监视器图案的掩模，所述聚焦监视器图案用于在晶片上形成第一和第二聚焦监视器标记，并且所述曝光监视器图案用于形成曝光 在晶片上获得聚焦监视标记的尺寸与散焦量之间的关系的曝光依赖性，在晶片上形成聚焦监视标记和曝光监视标记，测量曝光监视标记的尺寸以获得有效的 曝光，选择聚焦监视标记的尺寸与对应于有效曝光的散焦量之间的关系，测量第一和第二聚焦监视标记的尺寸，以及根据聚焦监视器的测量尺寸获得散焦量 标记和选择的关系。

公开(公告)号：US20060240341A1

公开(公告)日：2006-10-26

申请号：US11472452

申请日：2006-06-22

申请人： Kyoko Izuha ,  Hideki Kanai ,  Soichi Inoue ,  Shingo Kanamitsu ,  Shinichi Ito

发明人： Kyoko Izuha ,  Hideki Kanai ,  Soichi Inoue ,  Shingo Kanamitsu ,  Shinichi Ito

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G03F1/30 ,  G03F1/32 ,  G03F7/70641 ,  G03F7/70683

摘要： Disclosed is a mask comprising a first area including a first surrounding area in which a halftone phase shift film or a stacked film of a halftone phase shift film and an opaque film is provided on a transparent substrate, and a first opening area surrounded by the first surrounding area, and a second area including a second surrounding area in which a halftone phase shift film is provided on the transparent substrate and a second opening area surrounded by the second surrounding area, wherein a transparent film is provided in at least a part of the second opening area, the transparent film being configured to give a predetermined phase difference to exposure light passing through that part of the second opening area in which the transparent film is provided relative to exposure light passing through the second surrounding area.