公开(公告)号：US07835201B2

公开(公告)日：2010-11-16

申请号：US12152660

申请日：2008-05-14

Applicant: Guido De Sandre ,  Andrea Ambrosino ,  Marco Pasotti

Inventor： Guido De Sandre ,  Andrea Ambrosino ,  Marco Pasotti

IPC: G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  H03K3/35613

Abstract: A level-shifter circuit is adapted for shift an input voltage into an output voltage that is variable between a negative voltage value up to a preset positive voltage level. The shifter circuit includes a first circuit adapted to shift the input voltage into the preset positive voltage level, a second circuit adapted to transfer the preset voltage level to a third circuit connected to a preset negative voltage value. The third circuit is connected to a further voltage at a positive or nil level and is adapted to supply an output voltage to the preset negative level or to the positive or nil level.

Abstract translation: 电平移动器电路适于将输入电压转换成在负电压值直到预设的正电压电平之间可变的输出电压。 移位器电路包括适于将输入电压移动到预设正电压电平的第一电路，适于将预设电压电平传送到连接到预设负电压值的第三电路的第二电路。 第三电路以正电平或零电平连接到另一电压，并且适于将输出电压提供到预设的负电平或正电平或零电平。

公开(公告)号：US20090154249A1

公开(公告)日：2009-06-18

申请号：US12368271

申请日：2009-02-09

Applicant: Marco Pasotti ,  Guido De Sandre ,  David Iezzi ,  Marco Poles

Inventor： Marco Pasotti ,  Guido De Sandre ,  David Iezzi ,  Marco Poles

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14

Abstract: A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.

Abstract translation: 用于非易失性存储单元的读出放大器包括参考单元，连接到参考单元的第一负载和可连接到非易失性存储单元的第二负载，第一负载和第二负载都具有可控电阻; 所述第一负载和所述第二负载的控制电路以与所述第一负载的第一导通端子和所述第二导通端子之间的工作电压无关的方式向所述第一负载和所述第二负载提供控制电压。

公开(公告)号：US06894934B2

公开(公告)日：2005-05-17

申请号：US10728372

申请日：2003-12-04

Applicant: Fabio De Santis ,  Marco Pasotti ,  Guido De Sandre

Inventor： Fabio De Santis ,  Marco Pasotti ,  Guido De Sandre

IPC: G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C7/00 ,  G11C16/06

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C11/5642 ,  G11C16/28

Abstract: A sensing circuit for a memory cell includes a first bias current generator connected between a first voltage reference and a first inner circuit node, and a second reference current generator connected to the first voltage reference. A comparator having a first input terminal is connected to a comparison circuit node that is connected to the second reference current generator, a second input terminal is connected to a circuit node that is connected to the first inner circuit node, and an output terminal forms an output terminal of the sensing circuit. A cascode-configured bias circuit is connected between the inner circuit node and a matching circuit node. The cascode-configured bias circuit is also connected to a second voltage reference. A current/voltage conversion stage is connected to the matching circuit node, to the comparison circuit node, and to a third voltage reference.

Abstract translation: 用于存储单元的感测电路包括连接在第一电压基准和第一内部电路节点之间的第一偏置电流发生器和连接到第一参考电压的第二参考电流发生器。 具有第一输入端子的比较器连接到连接到第二参考电流发生器的比较电路节点，第二输入端子连接到连接到第一内部电路节点的电路节点，并且输出端子形成 输出端子。 在内部电路节点和匹配电路节点之间连接共源共栅偏置电路。 共源共栅配置的偏置电路也连接到第二电压基准。 电流/电压转换级连接到匹配电路节点，连接到比较电路节点和第三参考电压。

公开(公告)号：US20050005055A1

公开(公告)日：2005-01-06

申请号：US10768743

申请日：2004-01-29

Applicant: Marco Pasotti ,  Michele Borgatti ,  Pier Rolandi

Inventor： Marco Pasotti ,  Michele Borgatti ,  Pier Rolandi

IPC: G06F12/00 ,  G11C5/14 ,  G11C16/30

CPC classification number: G11C16/30

Abstract: An application-specific embeddable flash memory having three content-specific I/O ports and delivering a peak read throughput of 1.2 GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit having a programming rate of 1 Mbyte/s for non-volatile storage of code, data, and embedded FPGA bit stream configurations. The test chip uses a NOR-type 0.18 μm flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35 μm2.

Abstract translation: 具有三个特定于内容的I / O端口并具有1.2 GB / s的峰值读取吞吐量的特定于应用的嵌入式闪存。 该存储器与用于代码，数据和嵌入式FPGA位流配置的非易失性存储的具有1兆字节/秒的编程速率的专用自动编程门电压斜坡发生器电路组合。 测试芯片采用NOR型0.18 mum闪存嵌入式技术，具有1.8V电源，两个聚六金属和存储单元尺寸为0.35 mum <2>。

公开(公告)号：US06839818B2

公开(公告)日：2005-01-04

申请号：US10036088

申请日：2001-12-28

Applicant: Roberto Gastaldi ,  Gianbattsista Lo Giudice ,  Marco Pasotti ,  Federico Pio

Inventor： Roberto Gastaldi ,  Gianbattsista Lo Giudice ,  Marco Pasotti ,  Federico Pio

IPC: G11C16/10 ,  G06F12/00

CPC classification number: G11C16/102

Abstract: An electrically-modifiable, non-volatile, semiconductor memory comprising a plurality of user memory locations which can be addressed individually from outside the memory in order to read and to modify the data held therein is characterized in that, for each user memory location, there is a corresponding pair of physical memory locations in the memory, which assume, alternatively, the functions of an active memory location and of a non-active memory location, the active memory location containing a previously-written datum and the non-active memory location being available for the writing of a new datum to replace the previously-written datum, so that, upon a request to replace the previous datum with the new datum, the previous datum is kept in the memory until the new datum has been written.

Abstract translation: 一种可电气修改的非易失性半导体存储器，其包括多个用户存储器位置，其可以从存储器外部单独寻址以便读取和修改其中保存的数据，其特征在于，对于每个用户存储器位置， 存储器中的对应物理存储器位置对，其替代地假设有效存储器位置和非活动存储器位置的功能，所述活动存储器位置包含预先写入的数据和非活动存储器位置 可用于写入新的数据以替换以前写入的数据，以便在要求使用新数据替换以前的数据时，先前的数据保存在存储器中，直到新的数据被写入。

公开(公告)号：US06535428B2

公开(公告)日：2003-03-18

申请号：US09882535

申请日：2001-06-14

Applicant: Marco Pasotti ,  Guido De Sandre ,  Giovanni Guaitini ,  David Iezzi ,  Marco Poles ,  Michele Quarantelli ,  Pier Luigi Rolandi

Inventor： Marco Pasotti ,  Guido De Sandre ,  Giovanni Guaitini ,  David Iezzi ,  Marco Poles ,  Michele Quarantelli ,  Pier Luigi Rolandi

IPC: G11C1604

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/14 ,  G11C11/5642

Abstract: A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.

Abstract translation: 一种用于感测存储单元的感测电路，所述感测电路具有可电连接到所述存储单元以接收存储单元电流的第一电路分支，所述第一电路支路具有至少一个第一晶体管，当所述第一电路支路连接到 存储器单元基本上以共源共栅配置耦合到存储器单元。 偏置电流发生器与第一晶体管可操作地相关联，以迫使偏置电流流过其中。

公开(公告)号：US06473340B1

公开(公告)日：2002-10-29

申请号：US09699043

申请日：2000-10-27

Applicant: Marco Pasotti ,  Giovanni Guaitini ,  Pier Luigi Rolandi ,  Guido De Sandre

Inventor： Marco Pasotti ,  Giovanni Guaitini ,  Pier Luigi Rolandi ,  Guido De Sandre

IPC: G11C1300

CPC classification number: G11C11/5642 ,  G11C16/28

Abstract: A reading circuit having an array branch connected via an array bit line to an array memory cell, the content of which is to be read; a reference branch connected via a reference bit line to a current generator stage supplying a reference current; a current/voltage converter stage connected to the array branch and to the reference branch, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated to the currents flowing respectively in the array branch and in the reference branch; a comparator stage connected to the array node and the reference node for comparing the array and reference potentials; a sample and hold stage arranged between the array node and the comparator stage and selectively operable to sample and hold the array potential; and a switching off stage for switching off the array branch.

Abstract translation: 一种读取电路，具有经由阵列位线连接到阵列存储单元的阵列分支，其内容将被读取; 通过参考位线连接到提供参考电流的电流发生器级的参考支路; 连接到阵列支路和参考支路的电流/电压转换器级，并且在阵列节点和参考节点处分别提供与分别在阵列支路中流动的电流相关联的阵列电位和参考电位， 在参考分支中; 连接到阵列节点的比较器级和用于比较阵列和参考电位的参考节点; 布置在所述阵列节点和所述比较器台之间并且可选择地可操作地采样和保持所述阵列电位的采样和保持级; 以及用于关闭阵列分支的关闭阶段。

公开(公告)号：US06466481B1

公开(公告)日：2002-10-15

申请号：US09438232

申请日：1999-11-12

Applicant: Marco Pasotti ,  Roberto Canegallo ,  Giovanni Guaitini ,  Pier Luigi Rolandi

Inventor： Marco Pasotti ,  Roberto Canegallo ,  Giovanni Guaitini ,  Pier Luigi Rolandi

IPC: G11C1606

CPC classification number: G11C16/12

Abstract: The device comprises a current mirror circuit having a first and a second node connected, respectively, to a constant current source and to a drain terminal of a memory cell to be programmed. A voltage generating circuit is connected to the first node to bias it at a constant reference voltage (VR); an operational amplifier has an inverting input connected to the first node, a non-inverting input connected to the second node, and an output connected to the control terminal of the memory cell. Thereby, the drain terminal of the memory cell is biased at the constant reference voltage, having a value sufficient for programming, and the operational amplifier and the memory cell form a negative feedback loop that supplies, on the control terminal of the memory cell, a ramp voltage (VPCX) that causes writing of the memory cell. The ramp voltage increases with the same speed as the threshold voltage and can thus be used to know when the desired threshold value is reached, and thus when programming must be stopped. The presence of a bias transistor between the second node and the memory cell enables use of the same circuit also during reading.

Abstract translation: 该器件包括电流镜电路，其具有分别连接到待编程的存储器单元的恒定电流源和漏极端子的第一和第二节点。 电压产生电路连接到第一节点以将其以恒定的参考电压（VR）偏置; 运算放大器具有连接到第一节点的反相输入端，连接到第二节点的非反相输入端，以及连接到存储器单元的控制端子的输出端。 因此，存储单元的漏极端子被偏置在具有足以编程的值的恒定参考电压，并且运算放大器和存储单元形成负反馈回路，其在存储单元的控制端上提供 导致存储单元写入的斜坡电压（VPCX）。 斜坡电压以与阈值电压相同的速度增加，因此可以用于知道什么时候达到期望的阈值，并且因此当必须停止编程时。 在第二节点和存储器单元之间存在偏置晶体管，在读取期间也可以使用相同的电路。

公开(公告)号：US06195283B1

公开(公告)日：2001-02-27

申请号：US09076013

申请日：1998-05-11

Applicant: Pier Luigi Rolandi ,  Roberto Canegallo ,  Ernestina Chioffi ,  Danilo Gerna ,  Marco Pasotti

Inventor： Pier Luigi Rolandi ,  Roberto Canegallo ,  Ernestina Chioffi ,  Danilo Gerna ,  Marco Pasotti

IPC: G11C700

CPC classification number: G11C27/005

Abstract: For each memory cell to be programmed, the present threshold value of the cell is determined; the desired threshold value is acquired; the analog distance between the present threshold value and the desired threshold value is calculated; and a programming pulse is then generated, the duration of which is proportional to the analog distance calculated. The programming and reading cycle is repeated until the desired threshold is reached. By this means a time saving is obtained, owing to the reduction of the number of intermediate reading steps. The method permits programming in parallel and simultaneously of a plurality of cells of a memory array which is connected to a single word line and to different bit lines, each with a programming pulse the duration of which is proportional to the analog distance calculated for the same cell. The programming process is thus very fast, owing to parallel application of the programming and the saving in the intermediate reading cycles.

Abstract translation: 对于要编程的每个存储器单元，确定单元的当前阈值; 获取期望的阈值; 计算当前阈值与期望阈值之间的模拟距离; 然后产生编程脉冲，其持续时间与计算出的模拟距离成比例。 重复编程和读取周期，直到达到所需的阈值。 由于中间读取步骤数量的减少，可以节省时间。 该方法允许并行地编程存储器阵列的多个单元，其连接到单个字线和不同的位线，每个存储器阵列的编程脉冲的持续时间与为同一个字线计算的模拟距离成比例 细胞。 编程过程非常快，因为编程的并行应用和中间阅读周期的节省。

公开(公告)号：US6128228A

公开(公告)日：2000-10-03

申请号：US438823

申请日：1999-11-12

Applicant: Marco Pasotti ,  Roberto Canegallo ,  Giovanni Guaitini ,  Pier Luigi Rolandi

Inventor： Marco Pasotti ,  Roberto Canegallo ,  Giovanni Guaitini ,  Pier Luigi Rolandi

IPC: G11C11/56 ,  G11C16/28 ,  G11C27/00 ,  G11C13/00

CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5642 ,  G11C27/005

Abstract: An analog read circuit includes an output transistor connected to a memory cell to be read, and an operational amplifier having a non-inverting input connected to the drain terminal of the memory cell, an inverting input connected to a reference terminal, and an output, forming the output of the reading circuit and connected to the gate terminal of the output transistor. Bias transistors maintain the memory cell and the output transistor in the linear region, and the operational amplifier and the output transistor form a negative feedback loop so that the output voltage V.sub.O of the read circuit is linerly dependent upon the threshold voltage the memory cell. The reading circuit has high precision and high reading speed.

Abstract translation: 模拟读取电路包括连接到要读取的存储单元的输出晶体管，和具有连接到存储单元的漏极端子的非反相输入的运算放大器，连接到参考端子的反相输入端和输出端， 形成读出电路的输出并连接到输出晶体管的栅极端。 偏置晶体管将存储单元和输出晶体管保持在线性区域中，并且运算放大器和输出晶体管形成负反馈回路，使得读取电路的输出电压VO在线性地取决于存储器单元的阈值电压。 读取电路精度高，读取速度快。