公开(公告)号：US20130273714A1

公开(公告)日：2013-10-17

申请号：US13976486

申请日：2010-12-31

Applicant: Xing Wei ,  Zhongdang Wang ,  Fei Ye ,  Gongbai Cao ,  Chenglu Lin ,  Miao Zhang ,  Xi Wang

Inventor： Xing Wei ,  Zhongdang Wang ,  Fei Ye ,  Gongbai Cao ,  Chenglu Lin ,  Miao Zhang ,  Xi Wang

IPC: H01L21/02

CPC classification number: H01L21/3226 ,  H01L21/76254

Abstract: A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded.

Abstract translation: 通过沟槽工艺制备具有掩埋绝缘层的半导体衬底的方法包括以下步骤：提供器件衬底和支撑衬底; 在所述器件基板的表面上形成绝缘层; 在所述器件基板上进行加热处理，以在所述器件基板的表面上形成剥离区域; 将具有绝缘层的器件基板与支撑基板接合，使得绝缘层夹在器件基板和支撑基板之间; 退火和加强粘合界面，使得接合界面的粘附水平满足以下倒角研磨，减薄和抛光工艺中的要求; 在接合的器件基板上进行倒角研磨，变薄和抛光工艺。

公开(公告)号：US20130113926A1

公开(公告)日：2013-05-09

申请号：US13807964

申请日：2011-06-16

Applicant: Yingchun Chen ,  Lin Ye ,  Miao Zhang ,  Junfeng Ge ,  Lijuan Feng ,  Tiejun Liu ,  Feng Zhou

Inventor： Yingchun Chen ,  Lin Ye ,  Miao Zhang ,  Junfeng Ge ,  Lijuan Feng ,  Tiejun Liu ,  Feng Zhou

IPC: B64D15/20

CPC classification number: B64D15/20 ,  G06T7/0004 ,  G06T7/41 ,  G06T2207/30156

Abstract: A detecting device for detecting icing by an image includes an image acquiring system (1-A) and an image processing system (2-A). The image acquiring system (1-A) can acquire an image of an object's surface. The image processing system (2-A) can analyze the image and obtain an icing condition of the object's surface. The detecting device is simple and reliable. It can identify the category of the icing effectively. So, it can improve the accurateness of the icing detection significantly and can accomplish the detection of the object's whole surface. Furthermore, it can detect an icing condition of a super-cooled large droplet. A method for detecting an icing condition of an object's surface using the detecting device is also provided.

Abstract translation: 用于检测图像的结冰的检测装置包括图像获取系统（1-A）和图像处理系统（2-A）。 图像获取系统（1-A）可以获取对象表面的图像。 图像处理系统（2-A）可以分析图像并获得物体表面的结冰状况。 检测装置简单可靠。 它可以有效地识别结冰的类别。 因此，可以显着提高结冰检测的准确性，可以完成物体整体表面的检测。 此外，它可以检测超冷却大液滴的结冰状况。 还提供了一种使用检测装置检测物体表面的结冰状况的方法。

公开(公告)号：US08330228B2

公开(公告)日：2012-12-11

申请号：US12810694

申请日：2010-02-11

Applicant: Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

Inventor： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC: H01L27/092

CPC classification number: H01L27/1211 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/42392

Abstract: A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.

Abstract translation: Ge和Si混合材料反转模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有圆形截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在反相模式下，电流流过整个圆柱形通道，以实现高载流子迁移率，降低低频噪声，防止多晶硅栅极耗尽和短沟道效应，并增加器件的阈值电压。

公开(公告)号：US20120129320A1

公开(公告)日：2012-05-24

申请号：US13260757

申请日：2011-07-25

Applicant: Miao Zhang ,  Bo Zhang ,  Zhongying Xue ,  Xi Wang

Inventor： Miao Zhang ,  Bo Zhang ,  Zhongying Xue ,  Xi Wang

IPC: H01L21/20

CPC classification number: C30B29/52 ,  C30B1/00 ,  H01L21/28518 ,  H01L29/165 ,  H01L29/456

Abstract: The present invention discloses a method of NiSiGe epitaxial growth by introducing Al interlayer, comprising the deposition of an Al thin film on the surface of SiGe layer, subsequent deposition of a Ni layer on Al thin film and then the annealing process for the reaction between Ni layer and SiGe material of SiGe layer to form NiSiGe material. Due to the barrier effect of Al interlayer, NiSiGe layer features a single crystal structure, a flat interface with SiGe substrate and a thickness of up to 0.3 nm, significantly enhancing interface performance.

Abstract translation: 本发明公开了一种通过引入Al中间层的NiSiGe外延生长方法，包括在SiGe层的表面上沉积Al薄膜，随后在Al薄膜上沉积Ni层，然后在Ni之间进行退火处理 SiGe层的SiGe材料，形成NiSiGe材料。 由于Al中间层的阻挡效应，NiSiGe层具有单晶结构，与SiGe衬底的平坦界面，厚度可达0.3nm，显着提高了界面性能。

公开(公告)号：US20110254101A1

公开(公告)日：2011-10-20

申请号：US12810694

申请日：2010-02-11

Applicant: Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

Inventor： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC: H01L27/092

CPC classification number: H01L27/1211 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/42392

Abstract: A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.

Abstract translation: Ge和Si混合材料反转模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有圆形截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在反相模式下，电流流过整个圆柱形通道，以实现高载流子迁移率，降低低频噪声，防止多晶硅栅极耗尽和短沟道效应，并增加器件的阈值电压。

公开(公告)号：US20140057439A1

公开(公告)日：2014-02-27

申请号：US13591209

申请日：2012-08-21

Applicant: JIANDONG ZHANG ,  Han Chuan Fang ,  jianjun Zhang ,  Xiaowei Shu ,  MIAO ZHANG

Inventor： JIANDONG ZHANG ,  Han Chuan Fang ,  jianjun Zhang ,  Xiaowei Shu ,  MIAO ZHANG

IPC: H01L21/306

CPC classification number: H01L21/76801

Abstract: A method of forming interlayer dielectric comprising the steps of forming a first undoped layer, forming in-situ and sequentially a doped layer and a second undoped layer on the first undoped layer, and planarizing the second undoped layer.

Abstract translation: 一种形成层间电介质的方法包括以下步骤：形成第一未掺杂层，在第一未掺杂层上原位形成和依次形成掺杂层和第二未掺杂层，以及平坦化第二未掺杂层。

公开(公告)号：US08330229B2

公开(公告)日：2012-12-11

申请号：US12810740

申请日：2010-02-11

Applicant: Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

Inventor： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC: H01L27/092

CPC classification number: H01L27/1211 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/78696

Abstract: A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Si (110) and p-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an inversion mode, the devices have different orientation channels, the GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, and prevent polysilicon gate depletion and short channel effects.

Abstract translation: 混合取向反转模式GAA（Gate-All-Around）CMOSFET包括具有第一通道的PMOS区域，具有第二通道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由n型Si（110）和p型Si（100）形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 根据本发明的装置结构相当简单，紧凑且高度集成。 在反转模式中，器件具有不同的取向通道，GAA结构具有跑道形，高k栅介质层和金属栅极，从而实现高载流子迁移率，并防止多晶硅栅极耗尽和短沟道效应。

公开(公告)号：US20120112283A1

公开(公告)日：2012-05-10

申请号：US13002303

申请日：2010-12-16

Applicant: Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

Inventor： Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

IPC: H01L27/12 ,  H01L21/283

CPC classification number: H01L21/84 ,  H01L27/0255 ,  H01L27/1203

Abstract: The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness.

Abstract translation: 本发明公开了一种SOI CMOS电路中的ESD保护结构。 ESD保护结构包括各种纵向（垂直）PN结结构，其具有用于电流的显着扩大的接合面积。 所得到的装置实现了增加的大电流释放能力。 还公开了制造ESD保护纵向PN结的品种的工艺。 所公开的制造工艺与当前SOI技术的兼容性降低了实施成本并提高了集成度。

公开(公告)号：US20110254013A1

公开(公告)日：2011-10-20

申请号：US12810574

申请日：2010-02-11

Applicant: Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

Inventor： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

IPC: H01L27/092

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/42392

Abstract: A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.

Abstract translation: 混合取向累积模式GAA（Gate-All-Around）CMOSFET包括具有第一通道的PMOS区域，具有第二通道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由p型Si（110）和n型Si（100）形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 根据本发明的装置结构相当简单，紧凑且高度集成。 在积累模式中，电流流过整个跑道状通道。 所公开的装置导致高载流子迁移率。 同时防止多晶硅栅极耗尽和短沟道效应，并且阈值电压增加。

公开(公告)号：US20150194338A1

公开(公告)日：2015-07-09

申请号：US13825079

申请日：2012-09-25

Applicant: Zengfeng Di ,  Da Chen ,  Jiantao Bian ,  Zhongying Xue ,  Miao Zhang

Inventor： Zengfeng Di ,  Da Chen ,  Jiantao Bian ,  Zhongying Xue ,  Miao Zhang

IPC: H01L21/762 ,  H01L21/306

CPC classification number: H01L21/76254 ,  H01L21/30604 ,  H01L21/30625

Abstract: The present invention provides a method for preparing an ultra-thin material on insulator through adsorption by a doped ultra-thin layer. In the method, first, an ultra-thin doped single crystal film and an ultra-thin top film (or contains a buffer layer) are successively and epitaxially grown on a first substrate, and then a high-quality ultra-thin material on insulator is prepared through ion implantation and a bonding process. A thickness of the prepared ultra-thin material on insulator ranges from 5 nm to 50 nm. In the present invention, the ultra-thin doped single crystal film adsorbs the implanted ion, and a micro crack is then formed, so as to implement ion-cut; therefore, the roughness of a surface of a ion-cut material on insulator is small. In addition, an impurity atom strengthens an ion adsorption capability of the ultra-thin single crystal film, so that an ion implantation dose and the annealing temperature can be lowered in the preparation procedure, thereby effectively reducing the damage caused by the implantation to the top film, and achieving objectives of improving production efficiency and reducing the production cost.

Abstract translation: 本发明提供一种通过掺杂超薄层吸附制备绝缘体上的超薄材料的方法。 在该方法中，首先，在第一基板上依次外延生长超薄掺杂单晶膜和超薄顶膜（或包含缓冲层），然后在绝缘体上形成高品质超薄材料 通过离子注入和粘合工艺制备。 所制备的绝缘体上的超薄材料的厚度范围为5nm至50nm。 在本发明中，超薄掺杂单晶膜吸附注入的离子，然后形成微裂纹，从而实现离子切割; 因此，绝缘体上的离子切割材料的表面的粗糙度小。 此外，杂质原子增强了超薄单晶膜的离子吸附能力，使得在制备过程中可以降低离子注入剂量和退火温度，从而有效地减少了植入到顶部的损伤 电影，实现提高生产效率和降低生产成本的目标。