公开(公告)号：US20120112283A1

公开(公告)日：2012-05-10

申请号：US13002303

申请日：2010-12-16

申请人： Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

发明人： Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L27/12 ,  H01L21/283

CPC分类号： H01L21/84 ,  H01L27/0255 ,  H01L27/1203

摘要： The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness.

摘要翻译： 本发明公开了一种SOI CMOS电路中的ESD保护结构。 ESD保护结构包括各种纵向（垂直）PN结结构，其具有用于电流的显着扩大的接合面积。 所得到的装置实现了增加的大电流释放能力。 还公开了制造ESD保护纵向PN结的品种的工艺。 所公开的制造工艺与当前SOI技术的兼容性降低了实施成本并提高了集成度。

公开(公告)号：US08461651B2

公开(公告)日：2013-06-11

申请号：US13002303

申请日：2010-12-16

申请人： Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

发明人： Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L29/00

CPC分类号： H01L21/84 ,  H01L27/0255 ,  H01L27/1203

摘要： The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness.

摘要翻译： 本发明公开了一种SOI CMOS电路中的ESD保护结构。 ESD保护结构包括各种纵向（垂直）PN结结构，其具有用于电流的显着扩大的接合面积。 所得到的装置实现了增加的大电流释放能力。 还公开了制造ESD保护纵向PN结的品种的工艺。 所公开的制造工艺与当前SOI技术的兼容性降低了实施成本并提高了集成度。

公开(公告)号：US20120049262A1

公开(公告)日：2012-03-01

申请号：US13002320

申请日：2010-11-03

申请人： Xiaolu Huang ,  Jing Chen ,  Miao Zhang ,  Xi Wang

发明人： Xiaolu Huang ,  Jing Chen ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L29/78 ,  H01L21/8242 ,  B82Y99/00

CPC分类号： H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： A DRAM cell structure with extended trench, the DRAM cell structure comprises: a NMOS transistor and a trench capacitor connected with the source electrode of the NMOS transistor; the trench capacitor comprises: a semiconductor substrate; a multilayer structure as the bottom plate of the trench capacitor, formed over the semiconductor substrate, which is composed of N-type SiGe layers and N-type Si layers arranged alternatively; a trench formed through the multilayer structure deeply into the semiconductor substrate, whose sidewall cross section is serrate-shaped; a dielectric layer formed on the inner face of the trench; a first polycrystalline silicon layer which is filled in the trench as the top plate of the trench capacitor; and a P-type Si layer formed over the multilayer structure. The present invention adopts doping epitaxial growth process to fabricate a multilayer structure composed of N-type SiGe layers and N-type Si layers arranged alternatively as the bottom plate of the trench capacitor. Compared with the traditional buried plate, the fabricating process is simplified. In addition, the present invention adopts selective etching process to form a sidewall having a serrate-shaped cross section. This improved structure increases capacitor plate area and thus even thick dielectric layer will achieve required capacitance.

摘要翻译： 具有扩展沟槽的DRAM单元结构，DRAM单元结构包括：NMOS晶体管和与NMOS晶体管的源极连接的沟槽电容器; 所述沟槽电容器包括：半导体衬底; 作为沟槽电容器的底板的多层结构，形成在半导体衬底上，其由N型SiGe层和N型Si层交替排列; 通过多层结构形成的沟槽深入半导体衬底，其侧壁横截面是锯齿形的; 形成在所述沟槽的内表面上的电介质层; 填充在作为沟槽电容器的顶板的沟槽中的第一多晶硅层; 以及形成在所述多层结构上的P型Si层。 本发明采用掺杂外延生长工艺制造由N型SiGe层和N型Si层组成的多层结构，交替地配置为沟槽电容器的底板。 与传统的埋地板相比，制作工艺简单。 此外，本发明采用选择性蚀刻工艺来形成具有锯齿状横截面的侧壁。 这种改进的结构增加了电容器板面积，因此甚至厚的电介质层将实现所需的电容。

公开(公告)号：US20120021571A1

公开(公告)日：2012-01-26

申请号：US12937258

申请日：2010-07-14

申请人： Jing Chen ,  Xiaolu Huang ,  Jiexin Luo ,  Qingqing Wu ,  Xi Wang

发明人： Jing Chen ,  Xiaolu Huang ,  Jiexin Luo ,  Qingqing Wu ,  Xi Wang

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/66545 ,  H01L29/78615

摘要： The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process.

摘要翻译： 本发明公开了一种通过大的倾斜离子注入降低SOI MOS器件的浮体效应的方法，包括以下步骤：（a）将倾斜方向的离子注入到具有形成高掺杂P区的掩埋绝缘层的NMOS中 NMOS的源极区域和掩埋绝缘层之上，其中NMOS的纵向线与倾斜方向之间的角度为15至45度。 通过这种方法，源区下的高掺杂P区和高掺杂N区形成隧道结，以减少浮体效应。 此外，芯片面积不会增加，制造工艺简单，方法与常规CMOS工艺兼容。

公开(公告)号：US20120012931A1

公开(公告)日：2012-01-19

申请号：US13132879

申请日：2010-09-07

申请人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xiaolu Huang ,  Xi Wang

发明人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xiaolu Huang ,  Xi Wang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78615 ,  H01L29/458 ,  H01L29/78621

摘要： The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions, a silicide formed above the heavily doped N-type regions and the heavily doped P-type region, and a shallow N-type region which is contact to the silicide; an ohmic contact is formed between the heavily doped P-type region and the silicide thereon to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof without increasing the chip area and also overcome the disadvantages such as decreased effective channel width of the devices in the BTS structure of the prior art. The manufacturing method comprises steps of: forming a heavily doped P-type region via ion implantation, forming a metal layer above the source region and forming a silicide via the heat treatment between the metal layer and the Si underneath. The device in the present invention could be fabricated via simplified fabricating process with great compatibility with traditional CMOS technology.

摘要翻译： 本发明公开了一种具有BTS结构的SOI MOS器件及其制造方法。 SOI MOS器件的源极区域包括：两个重掺杂N型区域，形成在两个重掺杂N型区域之间的重掺杂P型区域，在重掺杂N型区域上形成的硅化物， 掺杂P型区域和与硅化物接触的浅N型区域; 在重掺杂的P型区域和其上的硅化物之间形成欧姆接触以释放积聚在SOI MOS器件的体区中的空穴，并且消除其浮体效应而不增加芯片面积，并且还克服了诸如降低有效性 现有技术的BTS结构中的设备的信道宽度。 该制造方法包括以下步骤：通过离子注入形成重掺杂的P型区，在源区上方形成金属层，并通过金属层与Si之间的Si之间的热处理形成硅化物。 本发明中的器件可以通过简化的制造工艺制造，与传统CMOS技术具有很好的兼容性。

公开(公告)号：US20110291191A1

公开(公告)日：2011-12-01

申请号：US12937360

申请日：2010-07-14

申请人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xiaolu Huang ,  Xi Wang

发明人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xiaolu Huang ,  Xi Wang

IPC分类号： H01L29/772

CPC分类号： H01L29/78612 ,  H01L21/266 ,  H01L29/1087 ,  H01L29/66772 ,  H01L29/78624

摘要： The present invention discloses a MOS structure with suppressed floating body effect including a substrate, a buried insulation layer provided on the substrate, and an active area provided on the buried insulation layer comprising a body region, a first conductive type source region and a first conductive type drain region provided on both sides of the body region respectively and a gate region provide on top of the body region, wherein the active area further comprises a highly doped second conductive type region between the first conductive type source region and the buried insulation layer. For manufacturing this structure, implant ions into a first conductive type source region via a mask having an opening thereon forming a highly doped second conductive type region under the first conductive type source region and above the buried insulation layer. The present invention will not increase chip area and is compatible with conventional CMOS process.

摘要翻译： 本发明公开了一种具有抑制的浮体效应的MOS结构，包括基板，设置在基板上的掩埋绝缘层，以及设置在掩埋绝缘层上的有源区，包括主体区，第一导电型源极区和第一导电 型漏极区域分别设置在主体区域的两侧，并且栅极区域提供在主体区域的顶部，其中有源区域还包括在第一导电型源极区域和掩埋绝缘层之间的高度掺杂的第二导电类型区域。 为了制造该结构，通过其上具有开口的掩模将离子注入到第一导电类型源区中，形成在第一导电类型源极区之下和掩埋绝缘层之上的高度掺杂的第二导电类型区。 本发明不会增加芯片面积并且与常规CMOS工艺兼容。

公开(公告)号：US20110221002A1

公开(公告)日：2011-09-15

申请号：US13055553

申请日：2010-07-14

申请人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Bingxu Ning ,  Zhongying Xue ,  Xiaolu Huang ,  Xi Wang

发明人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Bingxu Ning ,  Zhongying Xue ,  Xiaolu Huang ,  Xi Wang

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/0266

摘要： The present invention discloses a MOS ESD protection device for SOI technology and a manufacturing method for the device. The MOS ESD protection device comprises: an epitaxial silicon layer grown on top of an SOI substrate; a first side-wall spacer disposed on both sides of the epitaxial silicon layer so as to isolate the ESD protection device from the intrinsic active structures; a source region and a drain region disposed respectively on two sides of the epitaxial silicon layer; a poly silicon gate and a gate dielectric formed on top of the epitaxial silicon layer; and a second side-wall spacer disposed on both sides of the poly silicon gate of . ESD leakage current passes down to the SOI substrate for protection. Because ESD protection device and intrinsic MOS transistor are located in the same plane, this fabrication process can be inserted in the current MOS process flow.

摘要翻译： 本发明公开了一种用于SOI技术的MOS ESD保护器件和该器件的制造方法。 MOS ESD保护器件包括：在SOI衬底的顶部上生长的外延硅层; 设置在所述外延硅层的两侧的第一侧壁间隔件，以将所述ESD保护装置与所述固有活性结构隔离; 分别设置在所述外延硅层的两侧的源极区域和漏极区域; 形成在外延硅层顶部的多晶硅栅极和栅极电介质; 以及设置在多晶硅栅极两侧的第二侧壁间隔物。 ESD泄漏电流通过SOI衬底进行保护。 由于ESD保护器件和本征MOS晶体管位于同一平面内，所以该制造工艺可以插入当前的MOS工艺流程中。

公开(公告)号：US08937354B2

公开(公告)日：2015-01-20

申请号：US13128907

申请日：2010-09-08

申请人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Xiaolu Huang ,  Xi Wang

发明人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Xiaolu Huang ,  Xi Wang

IPC分类号： H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L21/266 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/42384 ,  H01L21/266 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/78612

摘要： The present invention discloses a PD SOI device with a body contact structure. The active region of the PD SOI device includes: a body region; a gate region, which is inverted-L shaped, formed on the body region; a N-type source region and a N-type drain region, formed respectively at the two opposite sides of the anterior part the body region; a body contact region, formed at one side of the posterior part of the body region, which is side-by-side with the N-type source region; and a first silicide layer, formed on the body contact region and the N-type source region, which is contact to both of the body contact region and the N-type source region. The body contact region of the device is formed on the border of the source region and the leading-out terminal of the gate electrode. It can suppress floating body effect of the PD SOI device meanwhile not increasing the chip area, thereby overcoming the shortcoming in the prior art that the chip area is enlarged when the traditional body contact structure is employed. Furthermore, the fabrication process provided herein is simple and compatible to the CMOS technology.

摘要翻译： 本发明公开了一种具有体接触结构的PD SOI器件。 PD SOI器件的有源区包括：主体区域; 形成在身体区域上的倒L形的栅极区域; 分别形成在身体区域的前部的两个相对侧的N型源极区域和N型漏极区域; 身体接触区域，形成在与N型源区并排的身体区域的后部的一侧; 以及形成在与所述本体接触区域和所述N型源极区域接触的所述本体接触区域和所述N型源极区域上的第一硅化物层。 器件的体接触区域形成在栅极电极的源极区域和引出端子的边界上。 它可以抑制PD SOI器件的浮体效应，同时不增加芯片面积，从而克服了现有技术中使用传统的体接触结构时芯片面积扩大的缺点。 此外，本文提供的制造工艺简单且与CMOS技术兼容。

公开(公告)号：US08710549B2

公开(公告)日：2014-04-29

申请号：US13128439

申请日：2010-09-07

申请人： Xiaolu Huang ,  Jing Chen ,  Xi Wang ,  Deyuan Xiao

发明人： Xiaolu Huang ,  Jing Chen ,  Xi Wang ,  Deyuan Xiao

IPC分类号： H01L29/66

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/78612

摘要： A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.

摘要翻译： 公开了一种用于消除浮体效应和自发热效应的SOI MOS器件。 该器件包括将有源栅极沟道耦合到Si衬底的连接层。 连接层在设备操作期间提供电气和热通道，可以消除浮体效应和自热效应。 详细公开了在Si活性通道和Si衬底之间具有SiGe连接器的MOS器件的实例，并提供制造工艺。

公开(公告)号：US08629029B2

公开(公告)日：2014-01-14

申请号：US13055577

申请日：2010-07-14

申请人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Jianhua Zhou ,  Xiaolu Huang ,  Xi Wang

发明人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Jianhua Zhou ,  Xiaolu Huang ,  Xi Wang

IPC分类号： H01L21/331

CPC分类号： H01L29/7317 ,  H01L29/66265

摘要： The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density. Furthermore, the present invention utilizes side-wall spacer process to improve the compatibility of SOI BJT and SOI CMOS, which simplifies the SOI BiCMOS process and thus reduce the cost.

摘要翻译： 本发明公开了一种垂直SOI双极结型晶体管及其制造方法。 双极结型晶体管包括从下到上的包括主体区域，掩埋氧化物层和顶部硅膜的SOI衬底; 位于由STI工艺形成的顶部硅膜中的有源区; 位于靠近由离子注入形成的掩埋氧化物层的有源区域的集电极区域; 位于靠近通过离子注入形成的顶部硅膜的深度的有源区域中的基极区域; 发射极和基极两者都位于基极区域之上; 位于发射极和基极周围的侧壁间隔物。 利用简单的双重多晶硅技术的本发明不仅可以改善晶体管的性能，而且可以减小有源区的面积，以增加集成密度。 此外，本发明利用侧壁间隔物工艺来改善SOI BJT和SOI CMOS的相容性，这简化了SOI BiCMOS工艺，从而降低了成本。