公开(公告)号：US10510721B2

公开(公告)日：2019-12-17

申请号：US15675214

申请日：2017-08-11

Applicant: Milind S. Bhagavat ,  Lei Fu ,  Ivor Barber ,  Chia-Ken Leong ,  Rahul Agarwal

Inventor： Milind S. Bhagavat ,  Lei Fu ,  Ivor Barber ,  Chia-Ken Leong ,  Rahul Agarwal

IPC: H01L25/065 ,  H01L23/29 ,  H01L23/498 ,  H01L23/528 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/36

Abstract: Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.

公开(公告)号：US20190326273A1

公开(公告)日：2019-10-24

申请号：US15961123

申请日：2018-04-24

Applicant: Milind S. Bhagavat ,  Rahul Agarwal ,  Gabriel H. Loh

Inventor： Milind S. Bhagavat ,  Rahul Agarwal ,  Gabriel H. Loh

IPC: H01L25/18 ,  H01L23/433 ,  H01L23/538 ,  H01L23/498 ,  H01L25/00

Abstract: Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

公开(公告)号：US10431517B2

公开(公告)日：2019-10-01

申请号：US15686558

申请日：2017-08-25

Applicant: John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H01L23/36 ,  H01L23/373

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US20190051633A1

公开(公告)日：2019-02-14

申请号：US15675214

申请日：2017-08-11

Applicant: Milind S. Bhagavat ,  Lei Fu ,  Ivor Barber ,  Chia-Ken Leong ,  Rahul Agarwal

Inventor： Milind S. Bhagavat ,  Lei Fu ,  Ivor Barber ,  Chia-Ken Leong ,  Rahul Agarwal

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/29 ,  H01L23/528

Abstract: Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.

公开(公告)号：US20120314367A1

公开(公告)日：2012-12-13

申请号：US13158802

申请日：2011-06-13

Applicant: Sam Ziqun ZHAO ,  Milind S. BHAGAVAT

Inventor： Sam Ziqun ZHAO ,  Milind S. BHAGAVAT

IPC: H05K7/20 ,  H01L21/02

CPC classification number: H01L23/36 ,  H01L23/467 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2924/15311 ,  H05K7/20172 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An apparatus for cooling a semiconductor element is provided. The apparatus can include an electron emitter configured to emit electrons such that at least some of the emitted electrons become attached to air particulates and an air accelerator configured to generate an electric field that accelerates the air particulates toward the air accelerator to create an air flow over at least a portion of the semiconductor element. The air flow carries heat away from the at least a portion of the semiconductor element.

Abstract translation: 提供一种用于冷却半导体元件的装置。 该装置可以包括被配置为发射电子的电子发射器，使得发射的电子中的至少一些变得附着到空气微粒，并且空气加速器被配置成产生电场，该空气加速空气微粒朝向空气加速器以产生空气流 半导体元件的至少一部分。 空气流从半导体元件的至少一部分携带热量。

公开(公告)号：US20120050989A1

公开(公告)日：2012-03-01

申请号：US13173456

申请日：2011-06-30

Applicant: Milind S. Bhagavat ,  Seyed Mahdi Saeidi ,  Tak Sang Yeung

Inventor： Milind S. Bhagavat ,  Seyed Mahdi Saeidi ,  Tak Sang Yeung

IPC: H05K7/20

CPC classification number: H01L23/467 ,  H01L23/3675 ,  H01L2924/0002 ,  H05K7/20136 ,  H05K7/20145 ,  H05K7/20154 ,  H01L2924/00

Abstract: Methods, systems, and apparatuses are described for cooling electronic devices. The electrical device includes an integrated circuit die (IC) having opposing first and second surfaces, a plurality of interconnects on the second surface of the IC die that enable the IC die to be coupled to a substrate, and a flexural plate wave device. The flexural plate wave device is configured to generate a stream of air to flow across the electrical device to cool the IC die during operation of the IC die.

Abstract translation: 描述了用于冷却电子设备的方法，系统和装置。 电气装置包括具有相对的第一和第二表面的集成电路管芯（IC），IC模头的第二表面上的使得IC管芯能够耦接到衬底的多个互连件，以及弯曲板形波装置。 弯曲板波装置被配置为产生流过电气装置的空气流，以在IC管芯的工作期间冷却IC管芯。

公开(公告)号：US07927185B2

公开(公告)日：2011-04-19

申请号：US12631929

申请日：2009-12-07

Applicant: Roland R. Vandamme ,  Milind S. Bhagavat

Inventor： Roland R. Vandamme ,  Milind S. Bhagavat

IPC: B24B49/00

CPC classification number: B24B37/28 ,  B24B7/228 ,  B24B49/02

Abstract: A method of processing a semiconductor wafer using a double side grinder of the type that holds the wafer in a plane with a pair of grinding wheels and a pair of hydrostatic pads. The method includes measuring a distance between the wafer and at least one sensor and determining wafer nanotopology using the measured distance. The determining includes using a processor to perform a finite element structural analysis of the wafer based on the measured distance.

Abstract translation: 使用将晶片保持在具有一对砂轮的平面中的类型的双面研磨机和一对静压垫来处理半导体晶片的方法。 该方法包括测量晶片与至少一个传感器之间的距离并使用所测量的距离来确定晶片纳米拓扑。 确定包括使用处理器基于测量的距离来执行晶片的有限元结构分析。

公开(公告)号：US07662023B2

公开(公告)日：2010-02-16

申请号：US11617430

申请日：2006-12-28

Applicant: Ronald D. Vandamme ,  Milind S. Bhagavat

Inventor： Ronald D. Vandamme ,  Milind S. Bhagavat

IPC: B24B49/00

CPC classification number: B24B37/28 ,  B24B7/228 ,  B24B49/02

Abstract: A double side grinder comprises a pair of grinding wheels and a pair of hydrostatic pads operable to hold a flat workpiece (e.g., semiconductor wafer) so that part of the workpiece is positioned between the grinding wheels and part of the workpiece is positioned between the hydrostatic pads. At least one sensor measures a distance between the workpiece and the respective sensor for assessing nanotopology of the workpiece. In a method of the invention, a distance to the workpiece is measured during grinding and used to assess nanotopology of the workpiece. For instance, a finite element structural analysis of the workpiece can be performed using sensor data to derive at least one boundary condition. The nanotopology assessment can begin before the workpiece is removed from the grinder, providing rapid nanotopology feedback. A spatial filter can be used to predict the likely nanotopology of the workpiece after further processing.

Abstract translation: 双面研磨机包括一对砂轮和一对静压垫，其可操作以保持平坦工件（例如，半导体晶片），使得工件的一部分位于砂轮之间并且部分工件位于静水压 垫 至少一个传感器测量工件和相应传感器之间的距离，用于评估工件的纳米拓扑学。 在本发明的方法中，在研磨期间测量与工件的距离，并用于评估工件的纳米拓扑学。 例如，可以使用传感器数据来执行工件的有限元结构分析以导出至少一个边界条件。 纳米技术评估可以在从研磨机上取出工件之前开始，提供快速的纳米拓扑反馈。 可以使用空间滤波器来进一步处理后预测工件的可能纳米拓扑。

公开(公告)号：US10714462B2

公开(公告)日：2020-07-14

申请号：US15961123

申请日：2018-04-24

Applicant: Milind S. Bhagavat ,  Rahul Agarwal ,  Gabriel H. Loh

Inventor： Milind S. Bhagavat ,  Rahul Agarwal ,  Gabriel H. Loh

IPC: H01L25/00 ,  H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L23/433 ,  H01L23/00

Abstract: Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

公开(公告)号：US20190371763A1

公开(公告)日：2019-12-05

申请号：US15991573

申请日：2018-05-29

Applicant: Rahul Agarwal ,  Milind S. Bhagavat

Inventor： Rahul Agarwal ,  Milind S. Bhagavat

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/78

Abstract: Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die of a third semiconductor wafer.