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公开(公告)号：US20110158403A1
公开(公告)日：2011-06-30
申请号：US12647459
申请日：2009-12-26
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , H04L9/3073 , H04L2209/24
摘要： Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one embodiment, logic generates a cipher key, in a second cycle, based on a previous cipher key, generated in a first cycle that immediately precedes the second cycle. Other embodiments are also described.
摘要翻译： 描述了为Galois Field（也称为有限场）加密和/或解密提供实时密钥计算的方法和装置。 在一个实施例中，逻辑在第二周期中基于在紧接在第二周期之前的第一周期中生成的先前密码密钥来生成密码密钥。 还描述了其它实施例。
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公开(公告)号：US20090168483A1
公开(公告)日：2009-07-02
申请号：US12006238
申请日：2007-12-31
CPC分类号： G11C11/419
摘要： Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described.
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公开(公告)号：US07379491B2
公开(公告)日：2008-05-27
申请号：US10744085
申请日：2003-12-24
申请人： Steven K. Hsu , Ram K. Krishnamurthy , Gian Gerosa
发明人： Steven K. Hsu , Ram K. Krishnamurthy , Gian Gerosa
IPC分类号： H04B3/36
CPC分类号： H04B3/36 , H03K3/35625
摘要： A system is provided that includes a clocking circuit to provide two repeater clock signals and a flop repeater circuit to receive the two repeater clock signals and an input data signal. The flop repeater circuit to provide an output data signal based on the two repeater clock signals. The flop repeater circuit including a plurality of transistors and inverters coupled together to function as a flip-flop circuit that passes data without any full transmission gates.
摘要翻译： 提供了一种系统，其包括用于提供两个中继器时钟信号的时钟电路和用于接收两个中继器时钟信号的触发中继器电路和输入数据信号。 触发中继器电路基于两个中继器时钟信号提供输出数据信号。 包括耦合在一起的多个晶体管和反相器的触发中继器电路用作在没有任何完全传输门的情况下传递数据的触发器电路。
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公开(公告)号：US07275204B2
公开(公告)日：2007-09-25
申请号：US10954648
申请日：2004-09-30
IPC分类号： H03M13/41
CPC分类号： H03M13/6505 , H03M13/41 , H03M13/4169
摘要： Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.
摘要翻译： 移位电阻环用于在维特比解码期间在追溯存储器中提供列访问。
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公开(公告)号：US07099219B2
公开(公告)日：2006-08-29
申请号：US11018012
申请日：2004-12-20
CPC分类号： G11C11/413 , G11C7/12 , G11C11/56
摘要： In some embodiment, a circuit is provided that comprises a bit line and bit cells coupled to the bit line. The bit line has an impedance. The bit cells, when operated, are each capable of adjusting the bit line impedance to indicate a stored bit value and a selected one of at least two read ports. Other embodiments are described or otherwise claimed herein.
摘要翻译： 在一些实施例中，提供了包括位线和耦合到位线的位单元的电路。 位线有阻抗。 位单元在操作时都能够调整位线阻抗以指示存储的位值和至少两个读端口中选择的一个。 在此描述或以其他方式要求保护的其它实施例。
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26.发明授权Low-power search line circuit encoding technique for content addressable memories 失效用于内容可寻址存储器的低功耗搜索线电路编码技术公开(公告)号：US07057913B2
公开(公告)日：2006-06-06
申请号：US10817941
申请日：2004-04-06
IPC分类号： G11C15/00
摘要： A circuit for searching a content addressable memory includes a driver which generates a plurality of search line values, different combinations of which are used to implement a one-hot encoding scheme for searching the memory. Two or more cells in the memory may be consecutive bit positions of a word, and the driver may be synchronously operated to generate the different combinations of values.
摘要翻译： 用于搜索内容可寻址存储器的电路包括产生多个搜索线值的驱动器，其中不同的组合用于实现用于搜索存储器的单热编码方案。 存储器中的两个或多个单元可以是字的连续位位置，并且可以同步地操作驱动器以产生不同的值组合。
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公开(公告)号：US06919737B2
公开(公告)日：2005-07-19
申请号：US10010737
申请日：2001-12-07
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018521
摘要： A voltage-level converter and a method of converting a first logic voltage level to a second logic voltage level are described. In one embodiment, a voltage-level converter connects a first logic unit connected to a first supply voltage to a second logic unit connected to a second supply voltage. The voltage-level converter includes at least one transistor connected to the second supply voltage. The at least one transistor has a threshold voltage whose absolute value is greater-than-or-about-equal to the absolute value of the difference between the second supply voltage and the first supply voltage. In an alternative embodiment, a method for converting a first logic voltage level to a second logic voltage level includes transmitting a logic signal from a logic unit having an output voltage swing of between a first voltage level and a second voltage level, receiving the logic signal at a logic circuit having a pull-up transistor and an output voltage swing between a third voltage level and a fourth voltage level, and turning off the pull-up transistor when the logic signal has a value slightly greater than the difference between the third voltage level and the first voltage level.
摘要翻译： 描述电压电平转换器和将第一逻辑电压电平转换到第二逻辑电压电平的方法。 在一个实施例中，电压电平转换器将连接到第一电源电压的第一逻辑单元连接到与第二电源电压连接的第二逻辑单元。 电压电平转换器包括连接到第二电源电压的至少一个晶体管。 所述至少一个晶体管具有其绝对值大于或等于所述第二电源电压和所述第一电源电压之间的差的绝对值的阈值电压。 在替代实施例中，用于将第一逻辑电压电平转换为第二逻辑电压电平的方法包括从具有在第一电压电平和第二电压电平之间的输出电压摆幅的逻辑单元传输逻辑信号，接收逻辑信号 在具有上拉晶体管的逻辑电路和在第三电压电平和第四电压电平之间的输出电压摆幅，并且当所述逻辑信号具有略大于所述第三电压 电平和第一电压电平。
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公开(公告)号：US06614279B2
公开(公告)日：2003-09-02
申请号：US09941457
申请日：2001-08-29
IPC分类号： H03F345
CPC分类号： G06F1/10
摘要： A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.
摘要翻译： 时钟接收器电路将从差分时钟分配介质接收的低幅度差分时钟信号分量转换成全摆幅数字时钟。 时钟接收器电路可以用作例如微电子器件内的管芯上的相关时钟分配系统的一部分。
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公开(公告)号：US06590801B2
公开(公告)日：2003-07-08
申请号：US10172106
申请日：2002-06-13
IPC分类号： G11C1140
CPC分类号： G11C11/412
摘要： Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.
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30.发明授权Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates 有权具有双输出产生能力的漏电保护器，用于深亚微米宽多米诺骨门公开(公告)号：US06549040B1
公开(公告)日：2003-04-15
申请号：US09608683
申请日：2000-06-29
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A circuit including a clock signal input to receive a clock signal, at least one data signal input to receive at least one data signal, and a multiple input conditional inverter to receive the clock signal and the data signal, and to generate a dynamic output. The circuit also includes a conditional keeper circuit to charge a dynamic output node when the clock is evaluating and the dynamic output is high.
摘要翻译： 一种电路，包括输入时钟信号以接收时钟信号，输入至少一个数据信号以接收至少一个数据信号，以及多输入条件反相器以接收时钟信号和数据信号，并产生动态输出。 电路还包括条件保持器电路，用于在时钟评估和动态输出为高时为动态输出节点充电。
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