公开(公告)号：US20060009959A1

公开(公告)日：2006-01-12

申请号：US11089588

申请日：2004-07-07

Applicant: Timothy Fischer ,  Rohit Bhatia

Inventor： Timothy Fischer ,  Rohit Bhatia

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/08

Abstract: Systems, methodologies, media, and other embodiments associated with activity factor based design are described. One exemplary system embodiment includes an activity factor logic configured to determine an activity factor for a first node. The activity factor relates an input activity for the first node to an output activity for the first node. The example system may also include a transmission factor logic configured to determine a transmission factor for the first node. The transmission factor describes a degree of causal power switching between the first node and a second node. The example system may also include a downstream power logic operably connected to the activity factor logic or the transmission factor logic. The downstream power logic may be configured to determine a power consumption amount for the second node. The power consumption amount may depend, for example, on the activity factor and the transmission factor.

Abstract translation: 描述了与基于活动因素的设计相关联的系统，方法，介质和其他实施例。 一个示例性系统实施例包括被配置为确定第一节点的活动因子的活动因素逻辑。 活动因素将第一节点的输入活动与第一个节点的输出活动相关联。 示例系统还可以包括被配置为确定第一节点的传输因子的传输因子逻辑。 传输因子描述了第一节点和第二节点之间的因果功率切换程度。 示例系统还可以包括可操作地连接到活动因子逻辑或传输因子逻辑的下游功率逻辑。 下游功率逻辑可以被配置为确定第二节点的功耗量。 功耗量可以取决于例如活动因素和传输因子。

公开(公告)号：US06591360B1

公开(公告)日：2003-07-08

申请号：US09484138

申请日：2000-01-18

Applicant: Donald C. Soltis, Jr. ,  Rohit Bhatia ,  Mark Gibson

Inventor： Donald C. Soltis, Jr. ,  Rohit Bhatia ,  Mark Gibson

IPC: G06F930

CPC classification number: G06F9/3838 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3867

Abstract: A method and apparatus that generates a simplified, localized version (“a local stall”) of a global stall to improve the performance of a pipelined microprocessor. The local stall is generated when a data-dependency hazard is detected for a local consumer. Utilizing circuitry used in the pipelined microprocessor's data-forwarding circuitry, the local stall is generated with a relatively minor increase in circuitry. The local stall is generated much sooner than the global stall, arriving much sooner in a local pipeline. The local pipeline utilizes the local stall to override the global stall, when appropriate, and to ensure that correct data is read for a local consumer and to operate more efficiently than a standard pipeline without a local stall.

Abstract translation: 一种产生全局失速的简化的局部版本（“局部失速”）以改进流水线微处理器的性能的方法和装置。 当本地消费者检测到数据依赖性危险时，会产生本地摊位。 利用流水线微处理器的数据转发电路中使用的电路，产生局部失速，电路相对较小。 当地的摊位比全球摊位早得多，早在一个地方管道中就快到了。 当地管道利用本地摊位在适当的时候覆盖全局摊位，并确保为当地消费者读取正确的数据，并且比没有本地摊位的标准流水线更有效地运行。

公开(公告)号：US06587940B1

公开(公告)日：2003-07-01

申请号：US09483774

申请日：2000-01-18

Applicant: Donald Charles Soltis, Jr. ,  Rohit Bhatia

Inventor： Donald Charles Soltis, Jr. ,  Rohit Bhatia

IPC: G06F930

CPC classification number: G06F9/3867 ,  G06F9/3828 ,  G06F9/3838

Abstract: A method and apparatus that utilizes a simplified, localized version (“a local data-dependency stall”) of a global data-dependency stall to avoid re-reading of a register file to improve the performance of a pipelined microprocessor. A non-asserted local data-dependency stall indicates that source operand for an instruction is correct. Accordingly, when a global data-dependency stall arrives, the instruction is stalled in a stage without re-reading the register file. Without the simplified, localized version of the global data-dependency stall, the source operand data is not known to be correct and is indeed assumed to be incorrect. Therefore, when the global data-dependency stall arrives, a complete re-computation of the source operand data must be performed, including a re-read of the register file. Likewise, an asserted local data-dependency stall indicates that source operand for an instruction is not correct. Accordingly, the instruction is stalled when the local data-dependency stall is asserted and until the data for the instruction is available. The available data is forwarded directly to the stalled instruction.

Abstract translation: 利用全局数据依赖性失速的简化的局部版本（“本地数据依赖性失速”）以避免重新读取寄存器文件以提高流水线微处理器的性能的方法和装置。 非断言的本地数据依赖失速指示指令的源操作数正确。 因此，当全局数据依赖性停止到达时，指令停止在一个阶段，而不重新读取寄存器文件。 没有简化的本地化版本的全局数据依赖性停滞，源操作数数据不知道是正确的，并且确实假定是不正确的。 因此，当全局数据依赖失速到达时，必须执行源操作数数据的完全重新计算，包括重新读取寄存器文件。 同样地，一个断言的本地数据依赖失速指示指令的源操作数不正确。 因此，当本地数据依赖失败被断言并且直到指令的数据可用时，指令被停止。 可用数据直接转发到停止的指令。

公开(公告)号：US09009630B2

公开(公告)日：2015-04-14

申请号：US13489165

申请日：2012-06-05

Applicant: Michael J. Kruzeniski ,  Joseph B. Tobens ,  Jon Bell ,  William Scott Stauber ,  Rohit Bhatia ,  Ram Pattabhi Papatla ,  Daniel Escapa

Inventor： Michael J. Kruzeniski ,  Joseph B. Tobens ,  Jon Bell ,  William Scott Stauber ,  Rohit Bhatia ,  Ram Pattabhi Papatla ,  Daniel Escapa

IPC: G06F3/048 ,  G06F3/0488 ,  G06F21/60 ,  G06F3/14

CPC classification number: G06F3/04883 ,  G06F21/604 ,  G06F21/6209 ,  G06F2221/2149

Abstract: A note-capture application is disclosed that allows notes to be displayed on the lock screen. In one embodiment, a note-capture application can be invoked when a mobile device is in an above-lock state. Note data can be captured using the note-capture application, and the captured data can be persistently displayed on the lock screen. A user can perform a unique gesture from the lock screen to invoke the note-capture application. In another embodiment, multiple input modes can be available for note data capture. For example, voice data, text data, camera data, etc. can all be used to capture notes for display on the lock screen.

Abstract translation: 公开了一种允许在锁屏上显示笔记的记录捕获应用程序。 在一个实施例中，当移动设备处于上述锁定状态时，可以调用音符捕获应用。 记录数据可以使用记录捕获应用程序进行捕获，捕获的数据可以持续显示在锁定屏幕上。 用户可以从锁定屏幕执行唯一的手势来调用音符捕获应用程序。 在另一个实施例中，多个输入模式可用于笔记数据捕获。 例如，语音数据，文本数据，相机数据等都可以用于捕获在锁屏幕上显示的笔记。

公开(公告)号：US07856636B2

公开(公告)日：2010-12-21

申请号：US11125859

申请日：2005-05-10

Applicant: Rohit Bhatia ,  Don C. Soltis, Jr.

Inventor： Rohit Bhatia ,  Don C. Soltis, Jr.

IPC: G06F9/46

CPC classification number: G06F9/526

Abstract: Systems and methods of sharing processing resources in a multi-threading environment are disclosed. An exemplary method may include allocating a lock value for a resource lock, the lock value corresponding to a state of the resource lock. A first thread may yield at least a portion of the processing resources for another thread. The resource lock may be acquired for the first thread if the lock value indicates the resource lock is available.

Abstract translation: 公开了在多线程环境中共享处理资源的系统和方法。 示例性方法可以包括为资源锁定分配锁定值，所述锁定值对应于所述资源锁定的状态。 第一个线程可以产生另一个线程的处理资源的至少一部分。 如果锁定值指示资源锁可用，则可以为第一线程获取资源锁。

公开(公告)号：US20070067602A1

公开(公告)日：2007-03-22

申请号：US11228058

申请日：2005-09-16

Applicant: James Callister ,  Eric Delano ,  Rohit Bhatia ,  Shawn Walker ,  Mark Gibson

Inventor： James Callister ,  Eric Delano ,  Rohit Bhatia ,  Shawn Walker ,  Mark Gibson

IPC: G06F12/00

CPC classification number: G06F12/1027 ,  G06F12/0842

Abstract: Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.

Abstract translation: 描述了与减轻上下文切换高速缓存和TLB未命中的影响相关联的系统，方法，媒体和其他实施例。 一个示例性系统实施例包括被配置为运行多处理虚拟存储器操作系统的处理器。 处理器可以可操作地连接到存储器，并且可以包括被配置为存储TLB条目的高速缓存和翻译后备缓冲器（TLB）。 示例性系统可以包括上下文控制逻辑，其被配置为选择性地将数据从TLB复制到数据存储器，用于从处理器交换出的第一进程，并且将数据从数据存储选择性地复制到TLB，以将第二进程交换到 到处理器。

公开(公告)号：US20060136286A1

公开(公告)日：2006-06-22

申请号：US11020447

申请日：2004-12-22

Applicant: Prashant Gupta ,  Kulo Rajasekaran ,  Liju Thomas ,  Derek LaSalle ,  Rohit Bhatia ,  Amit Kumar

Inventor： Prashant Gupta ,  Kulo Rajasekaran ,  Liju Thomas ,  Derek LaSalle ,  Rohit Bhatia ,  Amit Kumar

IPC: G06F17/30

CPC classification number: G06Q30/02 ,  G06Q30/0203 ,  G06Q30/0204

Abstract: The method may include creating a marketing campaign, selecting a list to receive the marketing campaign, allowing the user to modify the list selected, allowing the user to add a work item to the marketing campaign and executing the marketing campaign.

Abstract translation: 该方法可以包括创建营销活动，选择列表以接收营销活动，允许用户修改所选择的列表，允许用户向营销活动添加工作项并执行营销活动。

公开(公告)号：US20060031672A1

公开(公告)日：2006-02-09

申请号：US10910630

申请日：2004-08-03

Applicant: Donald Soltis ,  Rohit Bhatia ,  Eric DeLano ,  Bill Greene ,  Amy Santoni

Inventor： Donald Soltis ,  Rohit Bhatia ,  Eric DeLano ,  Bill Greene ,  Amy Santoni

IPC: H04L9/00

CPC classification number: G06F21/6281 ,  G06F12/1027 ,  G06F12/1491 ,  G06F2221/2105

Abstract: In one embodiment of the present invention, a computer-implemented method is provided for use in a computer system including a plurality of resources. The plurality of resources include protected resources and unprotected resources. The unprotected resources include critical resources and non-critical resources. The method includes steps of: (A) receiving a request from a software program to access a specified one of the unprotected resources; (B) granting the request if the computer system is operating in a non-protected mode of operation; and (C) if the computer system is operating in a protected mode of operation, performing a step of denying the request if the computer system is not operating in a protected diagnostic mode of operation.

Abstract translation: 在本发明的一个实施例中，提供了一种在包括多个资源的计算机系统中使用的计算机实现的方法。 多个资源包括受保护的资源和不受保护的资源。 未受保护的资源包括关键资源和非关键资源。 该方法包括以下步骤：（A）从软件程序接收访问指定的一个未受保护的资源的请求; （B）如果计算机系统以非保护操作模式运行，则授予请求; 以及（C）如果所述计算机系统以受保护的操作模式操作，则如果所述计算机系统未在受保护的诊断操作模式下操作，则执行拒绝所述请求的步骤。

公开(公告)号：US06823434B1

公开(公告)日：2004-11-23

申请号：US09510128

申请日：2000-02-21

Applicant: David P Hannum ,  Rohit Bhatia

Inventor： David P Hannum ,  Rohit Bhatia

IPC: G06F1200

CPC classification number: G11C7/20

Abstract: The present invention relates to a system and method for establishing an illegal system state for a table which is preferably fully associative to disable matching of prospective entries (entries to be written to the table) with entries already resident in the table. Preferably, disabling the matching of prospective and table entries forces a system for updating the fully associative table or array to employ a pointer system for writing prospective entries into the fully associative table. The illegal system may be invoked automatically upon powering up the system for updating the fully associative array or may be associated with a machine specific state effected upon issuing a specific command during program execution.

Abstract translation: 本发明涉及一种用于建立用于表的非法系统状态的系统和方法，该表优选完全关联以禁止与已经驻留在表中的条目匹配的预期条目（要写入表的条目）。 优选地，禁用预期和表格条目的匹配迫使更新完全关联表或数组的系统采用用于将预期条目写入完全关联表中的指针系统。 在系统上电时，可以自动调用非法系统来更新完全关联阵列，或者可能在程序执行期间发出特定命令时与机器特定状态相关联。

公开(公告)号：US06807625B1

公开(公告)日：2004-10-19

申请号：US09507032

申请日：2000-02-18

Applicant: Patrick Knebel ,  Mark Gibson ,  Rohit Bhatia ,  Kevin David Safford

Inventor： Patrick Knebel ,  Mark Gibson ,  Rohit Bhatia ,  Kevin David Safford

IPC: G06F1500

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30094 ,  G06F9/3842

Abstract: An apparatus and method for efficiently generating arithmetic flags in a computer system. The system includes an eflags register to stored partially computed flags computed by an arithmetic logic unit. The stored partial flags are computed in one cycle. The stored flags are decoded by one of two consuming instructions, PRODF or TBIT, in a second cycle.

Abstract translation: 一种用于在计算机系统中有效地产生算术标志的装置和方法。 该系统包括用于存储由算术逻辑单元计算的部分计算的标志的eflags寄存器。 存储的部分标志在一个周期内计算。 存储的标志在第二个周期中由两个消耗指令PRODF或TBIT中的一个解码。