公开(公告)号：US20250065440A1

公开(公告)日：2025-02-27

申请号：US18944314

申请日：2024-11-12

Applicant: ROHM CO., LTD.

Inventor： Kazunori FUJI

IPC: B23K26/082 ,  B23K26/21 ,  H01L23/00

Abstract: A joint structure includes a first and a second metal member overlapping with each other as viewed in a first direction. The first metal member and the second metal member are joined together. The joint structure includes a welded portion at which the first metal member and the second metal member, overlapping with each other, are partly fused to each other. The welded portion has an outer circumferential edge and a plurality of linear marks. The outer circumferential edge is annular as viewed in the first direction. The plurality of linear marks each extend from an inside of the welded portion toward the outer circumferential edge as viewed in the first direction. Each of the plurality of linear marks is curved to bulge to one sense of an annular direction along the outer circumferential edge.

公开(公告)号：US12225738B2

公开(公告)日：2025-02-11

申请号：US17787945

申请日：2021-01-15

Applicant: ROHM CO., LTD.

Inventor： Hirotaka Otake ,  Kentaro Chikamatsu

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/66

Abstract: A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode 22 of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer 21 of a ridge shape with the gate electrode 22 disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion 22A from an upper end to a thickness direction intermediate portion of the gate electrode 22 and a second etching step being a step differing in etching condition from the first etching step and being for forming a remaining second portion 22B of the gate electrode.

公开(公告)号：US12224654B2

公开(公告)日：2025-02-11

申请号：US17917661

申请日：2021-04-06

Applicant: Rohm Co., Ltd.

Inventor： Tsuyoshi Fukura ,  Daiki Yanagishima ,  Akio Sasabe

IPC: H02M1/08 ,  H02M1/00 ,  H03K19/0175

Abstract: A pulse receiving circuit constituting a signal transmission device includes a first pulse detector that receives a differential input between a first reception pulse signal, i.e. an internal signal at a secondary winding of a first transformer and a second reception pulse signal, i.e. an internal signal at a secondary winding of a second transformer; a second pulse detector that receives the differential input between the first reception pulse signal and the second reception pulse signal with input polarity reversed to that of the first pulse detector; and a logic unit that generates a reception pulse signal based on output signals of the first and second pulse detectors, respectively.

公开(公告)号：US20250048722A1

公开(公告)日：2025-02-06

申请号：US18789406

申请日：2024-07-30

Applicant: ROHM CO., LTD.

Inventor： Shoji TAKEI ,  Yuji KOGA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor device including a diode. The semiconductor device includes: a semiconductor substrate; an n-type diffusion region selectively formed in a surface layer portion of a p-type epitaxial layer; an n-type buried layer sandwiched between the semiconductor substrate and the n-type diffusion region and having an impurity concentration greater than that of the n-type diffusion region; a p-type anode contact region formed in a surface layer portion of a first main surface of the semiconductor substrate; an n-type first cathode contact region formed in a surface layer portion of the n-type diffusion region and in a surface layer portion of the first main surface; a p-type well region extending along a depth direction from the first main surface outside the first cathode contact region to reach the n-type buried layer, dividing the n-type diffusion region along a direction along the first main surface.

公开(公告)号：US20250047227A1

公开(公告)日：2025-02-06

申请号：US18793183

申请日：2024-08-02

Applicant: ROHM CO., LTD.

Inventor： Tatsuji NAKAI

IPC: H02P27/04 ,  H02P25/066

Abstract: A semiconductor integrated circuit device includes: a first terminal configured to receive a first voltage; a part of a charge pump circuit configured to output a second voltage obtained by stepping down the first voltage received from the first terminal; at least a part of a linear power supply circuit configured to output a third voltage obtained by stepping down the second voltage received from the charge pump circuit; an internal circuit configured to use the third voltage received from the linear power supply circuit as a power supply voltage; a second terminal configured such that a first end of an external resistor included in the charge pump circuit is connected to the second terminal; and a third terminal configured such that a second end of the external resistor is connected to the third terminal.

公开(公告)号：US20250046672A1

公开(公告)日：2025-02-06

申请号：US18923270

申请日：2024-10-22

Applicant: ROHM CO., LTD.

Inventor： Masashi HAYASHIGUCHI

IPC: H01L23/367 ,  H01L23/473

Abstract: A semiconductor module includes a cooling unit and a semiconductor device attached to the cooling unit. The cooling unit includes a housing and a heat dissipating member. The housing includes a recess and a bottom portion. The heat dissipating member is attached to the bottom portion and at least partly accommodated in the recess. The recess includes an inlet and an outlet. The semiconductor device includes a substrate that includes a heat dissipating layer covering the recess. The heat dissipating layer includes a base surface facing the recess and a depression recessed from the base surface. The depression overlaps with the recess in plan view.

公开(公告)号：US12218592B2

公开(公告)日：2025-02-04

申请号：US17896140

申请日：2022-08-26

Applicant: ROHM CO., LTD.

Inventor： Akihiro Kawano ,  Hiroaki Ando

IPC: H02M3/158 ,  H02M3/157 ,  H02M1/32

Abstract: A main comparator compares a feedback voltage VFB corresponding to an output voltage VOUT of a DC/DC converter with a reference voltage VREF and asserts a turn-on signal when the feedback voltage VFB falls below the reference voltage VREF. A timer circuit generates a turn-off signal S2 that transitions in level after an ON time TON proportional to (VOUT−VIN/VOUT has elapsed from assertion of the turn-on signal.

公开(公告)号：US12218187B2

公开(公告)日：2025-02-04

申请号：US18172830

申请日：2023-02-22

Applicant: ROHM CO., LTD.

Inventor： Yuki Nakano ,  Masaya Ueno ,  Sawa Haruyama ,  Yasuhiro Kawakami ,  Seiya Nakazawa ,  Yasunori Kutsuma

IPC: H01L29/04 ,  H01L21/04 ,  H01L21/761 ,  H01L21/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/872

Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

公开(公告)号：US12218124B2

公开(公告)日：2025-02-04

申请号：US18049731

申请日：2022-10-26

Applicant: ROHM Co., LTD.

Inventor： Toru Takuma ,  Adrian Joita ,  Shuntaro Takahashi

IPC: H03K17/06 ,  H01L27/02 ,  H01L29/78 ,  H02M3/156 ,  H03K17/082 ,  H03K19/0185 ,  H02M1/08

Abstract: Disclosed is a gate control circuit that generates a gate control signal of an output transistor connected between an application end of a power supply voltage and an application end of an output voltage. The gate control circuit includes a first current source connected between the application end of the power supply voltage and the application end of the output voltage, a second current source connected between an application end of a booster voltage and an application end of a reference voltage, the booster voltage being raised to a voltage value higher than the power supply voltage in a steady state, an output stage that uses at least one of the first and second current sources to generate a gate charge current for charging a gate of the output transistor, and a controller that uses at least one of the first and second current sources according to the output voltage.

公开(公告)号：US12217913B2

公开(公告)日：2025-02-04

申请号：US17950592

申请日：2022-09-22

Applicant: ROHM CO., LTD.

Inventor： Keisuke Fukae

IPC: H01G4/232 ,  H01G4/008 ,  H01G4/224 ,  H01G4/30 ,  H01L49/02

Abstract: The present disclosure provides a chip part. The chip part includes a substrate, a capacitor portion and a substrate body portion. The capacitor portion includes a plurality of wall portions having a lengthwise direction and separated from each other by a trench formed on a first main surface of the substrate. The substrate body portion is formed around the capacitor portion using a portion of the substrate. The plurality of wall portions are formed of a plurality of pillar units. The capacitor portion, in the plan view, includes a first capacitor portion and a second capacitor portion. The first capacitor portion includes the plurality of wall portions having the lengthwise direction as a first lengthwise direction. The second capacitor portion includes the plurality of wall portions having the lengthwise direction as a second lengthwise direction orthogonal to the first lengthwise direction.