公开(公告)号：US20130151820A1

公开(公告)日：2013-06-13

申请号：US13315380

申请日：2011-12-09

Applicant: Srikanth Arekapudi ,  Saurabh Gupta

Inventor： Srikanth Arekapudi ,  Saurabh Gupta

IPC: G06F9/302

CPC classification number: G06F9/30032 ,  G06F9/30018

Abstract: A method and apparatus are described for processing data during an execution pipeline cycle of a processor. Valid bits of the data are generated according to a designated data size. Each of the valid bits is inserted into at least one of a plurality of bit positions. The valid bits are rotated in a predetermined direction (i.e., left or right rotation) by a designated number of bit positions. Valid bits are removed from a portion of the plurality of bit positions after being rotated. Zeros or most significant bits (MSBs) of the data may be inserted in the bit positions from which the valid bits were removed. The number of bit positions to rotate the valid bits by may be designated by a first bit subset and a second bit subset. The first bit subset may indicate a number of bytes, and the second bit subset may indicate a number of bits.

Abstract translation: 描述了用于在处理器的执行流水线周期期间处理数据的方法和装置。 根据指定的数据大小生成数据的有效位。 每个有效位被插入到多个位位置中的至少一个中。 有效位沿预定方向（即左旋转或右旋转）旋转指定数量的位位置。 有效位在旋转后从多个位位置的一部分移除。 可以将数据的零或最高有效位（MSB）插入从其中去除有效位的位位置。 旋转有效位的位位置的数量可以由第一位子集和第二位子集指定。 第一比特子集可以指示多个字节，并且第二比特子集可以指示多个比特。

公开(公告)号：US20130088168A1

公开(公告)日：2013-04-11

申请号：US13691562

申请日：2012-11-30

Applicant: Tanuj Mohan ,  Premal Ashar ,  Saurabh Gupta

Inventor： Tanuj Mohan ,  Premal Ashar ,  Saurabh Gupta

IPC: G05B15/02 ,  H05B37/02

CPC classification number: G05B15/02 ,  G01S5/0027 ,  H05B37/02 ,  H05B37/0245

Abstract: Apparatuses, methods, apparatuses and systems for commissioning a light fixture are disclosed. One method includes receiving, by the light fixture, a message from a central controller, wherein reception of the message puts the light fixture into a known condition, establishing communication between the light fixture and a user, and communicating, by either the light fixture or the user, a location of the user at a time of the established communication, to the central controller, thereby allowing the central controller to record a location of the light fixture.

Abstract translation: 公开了用于调试灯具的设备，方法，设备和系统。 一种方法包括通过灯具接收来自中央控制器的消息，其中接收消息将灯具置于已知状态，建立灯具与用户之间的通信，并通过灯具或 用户，在建立的通信时的用户的位置，到中央控制器，从而允许中央控制器记录灯具的位置。

公开(公告)号：US08392735B2

公开(公告)日：2013-03-05

申请号：US13561412

申请日：2012-07-30

Applicant: Andrea Mucignat ,  Saurabh Gupta

Inventor： Andrea Mucignat ,  Saurabh Gupta

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  H04M2250/12 ,  H04W52/0254 ,  Y02D70/1222 ,  Y02D70/1224 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/23

Abstract: Systems and methods for processing motion sensor data using various power management modes of an electronic device are provided. Power may be provided to a motion sensor during a first power mode of the device. In response to the motion sensor detecting a motion event with a magnitude exceeding a threshold, the sensor may transmit a wake up signal to a power management unit of the device. In response to receiving the wake up signal, the power management unit may switch the device to a second power mode. The device may provide power to a processor and load the processor with a motion sensing application when switching to the second power mode. During the second power mode, motion sensor data may be processed to determine that the motion event is not associated with an intentional user input and the device may return to the first power mode.

Abstract translation: 提供了使用电子设备的各种电源管理模式来处理运动传感器数据的系统和方法。 可以在设备的第一功率模式期间向运动传感器提供功率。 响应于运动传感器检测到幅度超过阈值的运动事件，传感器可以向设备的功率管理单元发送唤醒信号。 响应于接收到唤醒信号，电源管理单元可以将设备切换到第二电源模式。 当切换到第二功率模式时，该设备可以向处理器提供电力并且在运动感测应用中加载处理器。 在第二功率模式期间，可以处理运动传感器数据以确定运动事件不与有意的用户输入相关联，并且设备可以返回到第一功率模式。

公开(公告)号：US08234512B2

公开(公告)日：2012-07-31

申请号：US12975558

申请日：2010-12-22

Applicant: Andrea Mucignat ,  Saurabh Gupta

Inventor： Andrea Mucignat ,  Saurabh Gupta

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3203 ,  H04M2250/12 ,  H04W52/0254 ,  Y02D70/1222 ,  Y02D70/1224 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/23

Abstract: Systems and methods for processing motion sensor data using various power management modes of an electronic device are provided. Power may be provided to a motion sensor during a first power mode of the device. In response to the motion sensor detecting a motion event with a magnitude exceeding a threshold, the sensor may transmit a wake up signal to a power management unit of the device. In response to receiving the wake up signal, the power management unit may switch the device to a second power mode. The device may provide power to a processor and load the processor with a motion sensing application when switching to the second power mode. During the second power mode, motion sensor data may be processed to determine that the motion event is not associated with an intentional user input and the device may return to the first power mode.

Abstract translation: 提供了使用电子设备的各种电源管理模式来处理运动传感器数据的系统和方法。 可以在设备的第一功率模式期间向运动传感器提供功率。 响应于运动传感器检测到幅度超过阈值的运动事件，传感器可以向设备的功率管理单元发送唤醒信号。 响应于接收到唤醒信号，电源管理单元可以将设备切换到第二电源模式。 当切换到第二功率模式时，该设备可以向处理器提供电力并且在运动感测应用中加载处理器。 在第二功率模式期间，可以处理运动传感器数据以确定运动事件不与有意的用户输入相关联，并且设备可以返回到第一功率模式。

公开(公告)号：US20120112763A1

公开(公告)日：2012-05-10

申请号：US12943379

申请日：2010-11-10

Applicant: Sandeep Kumar Goel ,  Saurabh Gupta ,  Wei-Pin Changchien ,  Chin-Chou Liu

Inventor： Sandeep Kumar Goel ,  Saurabh Gupta ,  Wei-Pin Changchien ,  Chin-Chou Liu

IPC: G01R23/20

CPC classification number: G01R31/318328

Abstract: System and method for effectively detecting small delay defects is disclosed. The method first loads layout information of an integrated circuit. Then, the nets and paths of the integrated circuit are partitioned into two groups based upon their physical information. The physical information comprises the length of each path and net and the number of vias at each path and net. A timing-aware automatic test pattern generator is configured to generate test patterns for the first group having paths and nets susceptible to small delay defects. A traditional transition delay fault test pattern generator is configured to generate test patterns for the second group.

Abstract translation: 公开了用于有效检测小延迟缺陷的系统和方法。 该方法首先加载集成电路的布局信息。 然后，基于它们的物理信息将集成电路的网络和路径划分成两组。 物理信息包括每个路径和网络的长度以及每个路径和网络处的通道数量。 定时感知自动测试模式发生器被配置为产生具有对小延迟缺陷敏感的路径和网络的第一组的测试模式。 传统的转换延迟故障测试模式发生器被配置为产生第二组的测试模式。

公开(公告)号：US07986591B2

公开(公告)日：2011-07-26

申请号：US12757396

申请日：2010-04-09

Applicant: Nan-Hsin Tseng ,  Chin-Chou Liu ,  Saurabh Gupta

Inventor： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Saurabh Gupta

IPC: G04F8/00 ,  G01R13/02

CPC classification number: G04F10/005

Abstract: An integrated circuit for high-resolution timing measurement includes a delay pulse generator, the first oscillator to generate the first clock with the first frequency, the second oscillator to generate the second clock with the second frequency, an oscillator tuner, a sampling module, a counter, wherein the delay pulse generator generated a delayed pulse from the second clock, the oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the second frequency, the sampling module samples the delayed pulse at the first frequency, the counter generates a digital counter value by counting a number of sampling by the sampling module, and a time width of the delayed pulse can be calculated by the digital counter value. The second oscillator can be a tunable ring oscillator with one or more coarse tune stages and one or more fine-tune stages.

Abstract translation: 用于高分辨率定时测量的集成电路包括延迟脉冲发生器，第一振荡器，用于产生具有第一频率的第一时钟，第二振荡器产生具有第二频率的第二时钟，振荡器调谐器，采样模块， 计数器，其中所述延迟脉冲发生器从所述第二时钟产生延迟脉冲，所述振荡器调谐器控制所述第二频率尽可能接近所述第一频率而不与所述第二频率相同，所述采样模块将所述延迟脉冲采样 第一频率，计数器通过对采样模块进行采样次数的计数来产生数字计数器值，并且可以通过数字计数器值计算延迟脉冲的时间宽度。 第二振荡器可以是具有一个或多个粗调级和一个或多个微调级的可调谐环形振荡器。

公开(公告)号：US07657775B1

公开(公告)日：2010-02-02

申请号：US11944429

申请日：2007-11-22

Applicant: Barry Wagner ,  Jonah M. Alben ,  Sonny Yeoh ,  Jeffrey J. Irwin ,  Saurabh Gupta

Inventor： Barry Wagner ,  Jonah M. Alben ,  Sonny Yeoh ,  Jeffrey J. Irwin ,  Saurabh Gupta

IPC: G06F1/00 ,  H03L7/00 ,  H03B5/12

CPC classification number: G06F1/3203 ,  G06F1/06 ,  G06F1/324 ,  Y02D10/126

Abstract: Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selected to provide a memory clock signal to the graphics memory. The multiplexer switches from providing a first clock source signal as the memory clock signal to providing a second clock source signal as the memory clock signal. The first clock source changes its frequency of operation. After the first clock source settles or stabilizes, the multiplexer switches back to providing the first clock source signal as the memory clock signal.

Abstract translation: 用于改变提供给图形存储器的时钟信号的频率的方法，电路和装置，同时减少监视器上的所得到的视觉毛刺或干扰。 具体实施例提供可以被多路复用或选择以提供存储器时钟信号给图形存储器的多个时钟源。 多路复用器从提供第一时钟源信号作为存储器时钟信号切换，以提供第二时钟源信号作为存储器时钟信号。 第一个时钟源改变其操作频率。 在第一个时钟源稳定或稳定后，多路复用器切换回提供第一个时钟源信号作为存储器时钟信号。

公开(公告)号：US07577813B2

公开(公告)日：2009-08-18

申请号：US11247036

申请日：2005-10-11

Applicant: Vijay B. Nijhawan ,  Saurabh Gupta ,  Bi-Chong Wang ,  Wuxian Wu

Inventor： Vijay B. Nijhawan ,  Saurabh Gupta ,  Bi-Chong Wang ,  Wuxian Wu

IPC: G06F12/00

CPC classification number: G06F12/0806 ,  G06F9/5016 ,  G06F2212/2542

Abstract: A system and method is disclosed for enumerating multi-level processor-memory affinities for non-uniform memory access systems. A processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in an information-handling system is calculated using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system. The information-handling system then performs an algorithm on each processor-memory affinity hierarchy to obtain processor-memory affinity values in the information-handling system, and populates a table using the processor-memory affinity values. An operating system in the information-handling system can use the table to allocate memory units among microprocessors in the information-handling system.

Abstract translation: 公开了一种用于枚举用于非均匀存储器访问系统的多级处理器 - 存储器亲和度的系统和方法。 使用描述如何将微处理器和存储器单元布置在信息处理系统中的存储器访问速度的至少两个特性来计算处理器 - 存储器亲和层次结构，用于信息处理系统中的微处理器和存储器单元的每个可能的配对。 处理系统。 然后，信息处理系统在每个处理器 - 存储器亲和层级上执行算法，以在信息处理系统中获得处理器 - 存储器相关性值，并且使用处理器 - 存储器亲和度值来填充表格。 信息处理系统中的操作系统可以使用该表来在信息处理系统中的微处理器之间分配存储单元。

公开(公告)号：US07539966B2

公开(公告)日：2009-05-26

申请号：US11502951

申请日：2006-08-11

Applicant: Tamal Basu ,  Saurabh Gupta ,  Tahir Malik ,  Hitesh Suri

Inventor： Tamal Basu ,  Saurabh Gupta ,  Tahir Malik ,  Hitesh Suri

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: Enhanced algorithms are provided for finding circuit edit locations which utilize automated conversions from circuit schematic to physical layout design. The enhanced algorithms further include a user interface enabling the user to provide preferences, limitations, and constraints in order to bias the search to be conducted, as well as using the provided design data in order to locate the best positions for particular edit schemes, including net cuts and net joins.

Abstract translation: 提供增强的算法用于查找电路编辑位置，利用从电路原理图到物理布局设计的自动转换。 增强算法还包括使得用户能够提供偏好，限制和约束的用户界面，以便偏移要进行的搜索，以及使用所提供的设计数据，以定位特定编辑方案的最佳位置，包括 净切割和网络连接。

公开(公告)号：US07530034B2

公开(公告)日：2009-05-05

申请号：US11363787

申请日：2006-02-27

Applicant: Martin Betz ,  Lokesh Johri ,  Rajesh Jain ,  Theodore R. Lundquist ,  Tamal Basu ,  Saurabh Gupta ,  Jagadish Narayana Gade

Inventor： Martin Betz ,  Lokesh Johri ,  Rajesh Jain ,  Theodore R. Lundquist ,  Tamal Basu ,  Saurabh Gupta ,  Jagadish Narayana Gade

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method and apparatus for defining a circuit operation, such as a charged particle beam operation to perform a circuit edit and define a probe point. Circuit operation definition is performed in a front-end environment with access to integrated circuit computer aided design tools providing logic level and layout level information concerning the integrated circuit. The front-end environment incorporates circuit operation optimization methods to identify optimal locations for a circuit operation. A back-end environment, such as a charged particle tool computing platform, is adapted to receive one or more files, which may include a truncated layout file with circuit operation location information, for use in further defining a circuit operation and/or performing the circuit operation.

Abstract translation: 一种用于定义电路操作的方法和装置，例如带电粒子束操作以执行电路编辑并定义探测点。 电路操作定义在前端环境中执行，可访问集成电路计算机辅助设计工具，提供有关集成电路的逻辑电平和布局级信息。 前端环境包含电路操作优化方法，以确定电路操作的最佳位置。 诸如带电粒子工具计算平台的后端环境适于接收一个或多个文件，其可以包括具有电路操作位置信息的截断的布局文件，以用于进一步定义电路操作和/或执行 电路操作。