公开(公告)号：US08384146B2

公开(公告)日：2013-02-26

申请号：US13428848

申请日：2012-03-23

Applicant: Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

Inventor： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

IPC: H01L29/76

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/792

Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

Abstract translation: 公开了制造具有间隔层的半导体存储单元的方法。 一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层 在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。 该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。 在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

公开(公告)号：US20110156130A1

公开(公告)日：2011-06-30

申请号：US13044313

申请日：2011-03-09

Applicant: Michael BRENNAN ,  Scott BELL

Inventor： Michael BRENNAN ,  Scott BELL

IPC: H01L29/772 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L27/115 ,  H01L21/0338 ,  H01L21/3088 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66795

Abstract: A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures.

Abstract translation: 在半导体器件中形成多个导电结构的方法包括在掩模的侧表面附近形成间隔物，其中掩模和间隔物形成在导电层上。 该方法还包括蚀刻未被间隔物或掩模覆盖的导电层的一部分中的至少一个沟槽。 该方法还可以包括在半导体器件上沉积材料，去除掩模并蚀刻导电层以去除未被间隔物或材料覆盖的导电层的部分，其中导电层的其余部分形成导电结构。

公开(公告)号：US07928005B2

公开(公告)日：2011-04-19

申请号：US11235214

申请日：2005-09-27

Applicant: Michael Brennan ,  Scott Bell

Inventor： Michael Brennan ,  Scott Bell

IPC: H01L21/44

CPC classification number: H01L27/115 ,  H01L21/0338 ,  H01L21/3088 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66795

Abstract: A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures.

Abstract translation: 在半导体器件中形成多个导电结构的方法包括在掩模的侧表面附近形成间隔物，其中掩模和间隔物形成在导电层上。 该方法还包括蚀刻未被间隔物或掩模覆盖的导电层的一部分中的至少一个沟槽。 该方法还可以包括在半导体器件上沉积材料，去除掩模并蚀刻导电层以去除未被间隔物或材料覆盖的导电层的部分，其中导电层的其余部分形成导电结构。

公开(公告)号：US07498222B1

公开(公告)日：2009-03-03

申请号：US11371024

申请日：2006-03-09

Applicant: John C. Foster ,  Scott Bell ,  Allison Holbrook ,  Simon S. Chan ,  Phillip Jones

Inventor： John C. Foster ,  Scott Bell ,  Allison Holbrook ,  Simon S. Chan ,  Phillip Jones

IPC: H01L21/336

CPC classification number: H01L29/792 ,  H01L29/513 ,  H01L29/66833

Abstract: A high K layer, such as aluminum oxide or hafnium oxide, may be formed with a deposition process that uses an ion implantation to damage portions of the high K material that are to be later etched. More particularly, in one implementation, a semiconductor device is manufactured by forming a first dielectric over a substrate, forming a charge storage element over the first dielectric, forming a second dielectric above the charge storage element, implantation ions into select portions of the second dielectric, and etching the ion implanted select portions of the second dielectric.

Abstract translation: 可以用沉积工艺形成高K层，例如氧化铝或氧化铪，所述沉积工艺使用离子注入来破坏将被蚀刻的高K材料的部分。 更具体地，在一个实施方式中，通过在衬底上形成第一电介质来形成半导体器件，在第一电介质上形成电荷存储元件，在电荷存储元件上形成第二电介质，将离子注入第二电介质的选择部分 并蚀刻第二电介质的离子注入选择部分。

公开(公告)号：USD562118S1

公开(公告)日：2008-02-19

申请号：US29236375

申请日：2005-08-16

Applicant: Jeffrey Scott Bell ,  Allan Patrick Smith ,  Gary Phillip Greenway

Designer： Jeffrey Scott Bell ,  Allan Patrick Smith ,  Gary Phillip Greenway

公开(公告)号：US20070222604A1

公开(公告)日：2007-09-27

申请号：US11387176

申请日：2006-03-23

Applicant: William Phipps ,  Alberto Rodriguez ,  Scott Bell ,  Heiko Rommelmann

Inventor： William Phipps ,  Alberto Rodriguez ,  Scott Bell ,  Heiko Rommelmann

IPC: G08B13/14

CPC classification number: G06K19/07749 ,  G06K7/0008 ,  G06K7/10178

Abstract: An RFID bridge antenna is positioned between a tag antenna associated with a tag and a reader antenna associated with a reader. The bridge includes at least two RF antenna elements spaced apart from one another and coupled together by an electrical conductor. The first RF antenna element is located proximate to the tag antenna and the second RF antenna element is located proximate to the reader antenna. An electromagnetic carrier signal transmitted by the reader antenna is received by one of the RF antenna element and retransmitted to the tag antenna by the other RF antenna element, increasing the distance over which the tag can communicate with the reader. Where the tag is attached to a packaged object, the RFID bridge antenna may be included in the package to allow wireless data communication between the tag and a reader. The reader may also be located external to the package. For example, one of the RF antenna elements may be attached to a label on the package, allowing data stored in the tag to be extracted by the external reader. The object may be a module, also known as a customer replaceable unit (CRU), and the tag may be configured as a customer replaceable unit monitor (CRUM).

Abstract translation: RFID桥接天线位于与标签相关联的标签天线和与读取器相关联的读取器天线之间。 该桥包括彼此间隔开并通过电导体耦合在一起的至少两个RF天线元件。 第一RF天线元件位于标签天线附近，第二RF天线元件位于读取器天线附近。 由读取器天线发送的电磁载波信号由RF天线元件中的一个接收，并由另一个RF天线元件重传到标签天线，从而增加标签可与读取器通信的距离。 在标签连接到打包对象的地方，RFID桥接天线可以包括在包装中，以允许标签和读取器之间的无线数据通信。 阅读器也可以位于包装的外部。 例如，RF天线元件中的一个可以附接到包装上的标签，从而允许由外部读取器提取存储在标签中的数据。 对象可以是模块，也称为客户可更换单元（CRU），并且标签可以被配置为客户可更换单元监视器（CRUM）。

公开(公告)号：USD541622S1

公开(公告)日：2007-05-01

申请号：US29189112

申请日：2003-08-29

Applicant: Jeffrey Scott Bell ,  Allan Patrick Smith ,  Gary Phillip Greenway

Designer： Jeffrey Scott Bell ,  Allan Patrick Smith ,  Gary Phillip Greenway

公开(公告)号：USD528899S1

公开(公告)日：2006-09-26

申请号：US29234226

申请日：2005-07-15

Applicant: Jeffrey Scott Bell ,  Allan Patrick Smith ,  Gary Phillip Greenway

Designer： Jeffrey Scott Bell ,  Allan Patrick Smith ,  Gary Phillip Greenway

公开(公告)号：US20060133609A1

公开(公告)日：2006-06-22

申请号：US11012478

申请日：2004-12-16

Applicant: Alberto Rodriguez ,  Heiko Rommelmann ,  Scott Bell ,  Will Phipps ,  Ron Boucher

Inventor： Alberto Rodriguez ,  Heiko Rommelmann ,  Scott Bell ,  Will Phipps ,  Ron Boucher

IPC: H04N7/167

CPC classification number: G11B20/00275 ,  G06F2221/2121 ,  G11B20/00086 ,  G11B20/00876

Abstract: An authentication apparatus includes a reading or recording medium equipped with an authentication tag, and a reading and recording drive that includes a transmitter and a coupler chip, wherein the authentication tag and the transmitter are capable of communicating with each other when the reading medium or the recording medium is coupled to the reading and recording drive. An authentication method includes providing a reading medium or a recording medium with an authentication tag, providing a reading and/or recording drive with a transmitter and a communication interface wherein the authentication tag and the transmitter are capable of communicating with each other when the reading medium or recording medium is coupled to the reading and/or recording drive, and authenticating the reading medium or recording medium via a communication between the authentication tag and the transmitter.

Abstract translation: 认证装置包括配备有认证标签的读取或记录介质以及包括发送器和耦合器芯片的读取和记录驱动器，其中当读取介质或者读取介质时，认证标签和发送器能够彼此通信 记录介质耦合到读取和记录驱动器。 认证方法包括向读取介质或记录介质提供认证标签，向发送器和通信接口提供读取和/或记录驱动器，其中认证标签和发送器能够在读取介质 或记录介质耦合到读取和/或记录驱动器，并且通过认证标签和发送器之间的通信来认证读取介质或记录介质。

公开(公告)号：US07005386B1

公开(公告)日：2006-02-28

申请号：US10656467

申请日：2003-09-05

Applicant: Scott Bell ,  Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Ashok M. Khathuria

Inventor： Scott Bell ,  Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Ashok M. Khathuria

IPC: H01L21/302

CPC classification number: H01L21/32139 ,  H01L21/0274 ,  H01L21/31058

Abstract: According to one exemplary embodiment, a method for reducing resist height erosion in a gate etch process comprises a step of forming a first resist mask on an anti-reflective coating layer situated over a substrate, where the first resist mask has a first width. The anti-reflective coating layer may be, for example, an organic material. The method further comprises a step of trimming the first resist mask to form a second resist mask, where the second resist mask has a second width, and where the second width is less than the first width. The step of trimming the first resist mask may further comprise, for example, etching the anti-reflective coating layer. According to this exemplary embodiment, the method further comprises a step of performing an HBr plasma treatment on the second resist mask, wherein the HBr plasma treatment causes a vertical etch rate of the second resist mask to decrease.

Abstract translation: 根据一个示例性实施例，用于降低栅极蚀刻工艺中的抗蚀剂高度腐蚀的方法包括在位于衬底上的抗反射涂层上形成第一抗蚀剂掩模的步骤，其中第一抗蚀剂掩模具有第一宽度。 抗反射涂层可以是例如有机材料。 该方法还包括修整第一抗蚀剂掩模以形成第二抗蚀剂掩模的步骤，其中第二抗蚀剂掩模具有第二宽度，并且其中第二宽度小于第一宽度。 修整第一抗蚀剂掩模的步骤还可以包括例如蚀刻抗反射涂层。 根据该示例性实施例，该方法还包括在第二抗蚀剂掩模上执行HBr等离子体处理的步骤，其中HBr等离子体处理导致第二抗蚀剂掩模的垂直蚀刻速率降低。