公开(公告)号：US07781287B2

公开(公告)日：2010-08-24

申请号：US12022329

申请日：2008-01-30

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US20080124869A1

公开(公告)日：2008-05-29

申请号：US12022329

申请日：2008-01-30

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US07348628B2

公开(公告)日：2008-03-25

申请号：US11448437

申请日：2006-06-07

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级上的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US20070250934A1

公开(公告)日：2007-10-25

申请号：US11628048

申请日：2005-05-31

申请人： Seung-Bae Park

发明人： Seung-Bae Park

IPC分类号： G06F17/00

CPC分类号： G06F21/36

摘要： A method for preventing input information from exposing to observers is disclosed. The information input method according to the present invention provides an action symbol group, a non-action symbol group and a control tool group through a secret information input unit. Users input their desirable information to the action symbol group, as one of movement operation, disappear operation and symbol value increment (decrement) operation is conducted. Although observers watch information input processes, since the information input method of the present invention does not allow the observers to recognize the inputted information, it can basically prevent input information from exposing to observers.

摘要翻译： 公开了一种防止输入信息暴露给观察者的方法。 根据本发明的信息输入方法通过秘密信息输入单元提供动作符号组，非动作符号组和控制工具组。 用户将其理想信息输入到动作符号组中，作为移动操作，消失操作和符号值递增（递减）操作之一。 虽然观察者观看信息输入处理，但是由于本发明的信息输入方法不允许观察者识别输入的信息，所以基本上可以防止输入信息暴露给观察者。

公开(公告)号：US20070152255A1

公开(公告)日：2007-07-05

申请号：US11600568

申请日：2006-11-16

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L29/94

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F 2结构，并且可以应用传统的线和接触形成工艺，使得容易制造高度集成的半导体存储器件

公开(公告)号：US20070012996A1

公开(公告)日：2007-01-18

申请号：US11448437

申请日：2006-06-07

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L31/00 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级上的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US20120273898A1

公开(公告)日：2012-11-01

申请号：US13549648

申请日：2012-07-16

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L27/088

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，使得容易制造高度集成的半导体存储器件

公开(公告)号：US08022457B2

公开(公告)日：2011-09-20

申请号：US11600568

申请日：2006-11-16

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L29/94

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，从而容易地制造高度集成的半导体存储器件。

公开(公告)号：US07860850B2

公开(公告)日：2010-12-28

申请号：US11707342

申请日：2007-02-16

申请人： Seung Bae Park

发明人： Seung Bae Park

IPC分类号： G06F7/00 ,  G06F21/22

CPC分类号： G06F21/562

摘要： Scanning engine (i.e. program(s) or application(s)) 310 sends request 315 to direct file system access engine (i.e. program(s) or application(s)) 360. Direct file system access engine 360 receives request 315 and passes request 315 to file system(s) 350 as request 325. No filter program(s) 340 receive program control as request 325 bypasses any filter program(s) 340. The direct file system access engine 360 receives unaltered information from file system(s) 350. Utilising Direct File Access (DFA) allows bypass of user mode hooking-type malwares, kernel, and file system filter programs to obtain access to or communicate with the real underlying file system(s). This provides a ‘clean’ view of the file system(s) in situations where user/kernel components are compromised or rootkit file system filter programs are installed.

摘要翻译： 扫描引擎（即程序或应用程序）310向直接文件系统访问引擎（即程序或应用程序）发送请求315.直接文件系统访问引擎360接收请求315并通过请求 请求325接收程序控制。请求325绕过任何过滤程序340.直接文件系统访问引擎360从文件系统340接收未更改的信息。 350.利用直接文件访问（DFA）允许绕过用户模式挂钩型恶意软件，内核和文件系统过滤程序，以获得对真实底层文件系统的访问或与其通信。 在安装用户/内核组件或rootkit文件系统过滤程序的情况下，这将提供文件系统的“干净”视图。

公开(公告)号：US07814549B2

公开(公告)日：2010-10-12

申请号：US11499463

申请日：2006-08-04

申请人： Seung Bae Park

发明人： Seung Bae Park

IPC分类号： G06F12/14

CPC分类号： G06F21/57

摘要： A method, computer program product and system for obtaining notification information about the state of an operating system. The method includes the steps of receiving, by a Direct Process Access (DPA) engine, a request for the notification information from a requesting program. The notification information is obtained from a database associated with the DPA engine and the notification information is provided to the requesting program. The DPA engine receives update information indicative of changes in the notification information directly from the operating system and causes the notification information to be updated in the database.

摘要翻译： 一种用于获取关于操作系统的状态的通知信息的方法，计算机程序产品和系统。 该方法包括以下步骤：通过直接过程访问（DPA）引擎从请求程序接收对通知信息的请求。 从与DPA引擎相关联的数据库获得通知信息，并且向请求程序提供通知信息。 DPA引擎直接从操作系统接收指示通知信息的变化的更新信息，并且使得在数据库中更新通知信息。