公开(公告)号：US06370655B1

公开(公告)日：2002-04-09

申请号：US09174676

申请日：1998-10-19

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G06F1120

CPC classification number: G06F9/445 ,  G06F11/1433

Abstract: A computer system is provided that loads a computer program, in a reverse order, into a memory device having one or more defective memory cells. The program is organized into code modules with each code module including at least one complete instruction, or data block. The last code module of the program is loaded first into the last or highest addresses of the address space allocated in the memory for the program. Thereafter, the code module preceding the last loaded code module of the program is loaded into the addresses preceding the previously-loaded addresses. The subsequent code modules are loaded into successively lower memory addresses in a reverse fashion until the first code module of the program is loaded into memory. As each code module, or the codes that make up the code module, are loaded, each loaded memory address is checked for a defective cell. A JUMP instruction is created and inserted into the original program code preceding the defective memory address to bypass any defective memory cell without interrupting the intended operation of the instruction steps that are loaded into the memory. In addition, a JUMP instruction is inserted into the memory start address so that a processor is forced to begin execution at the memory address containing the first byte of the first code module. Certain byte codes that include referenced addresses are then modified to correct any address-referencing that may be changed due to the insertion of the JUMP instructions, and then loaded into the appropriate addresses in the memory.

Abstract translation: 提供了一种计算机系统，其以相反的顺序将计算机程序加载到具有一个或多个有缺陷的存储器单元的存储器件中。 该程序被组织成代码模块，每个代码模块包括至少一个完整指令或数据块。 程序的最后一个代码模块首先加载到程序存储器中分配的地址空间的最后或最高地址。 此后，程序的最后加载的代码模块之前的代码模块被加载到先前加载的地址之前的地址中。 随后的代码模块以相反的方式加载到连续较低的存储器地址中，直到程序的第一代码模块被加载到存储器中。 由于每个代码模块或构成代码模块的代码都被加载，所以检查每个加载的存储器地址是否有缺陷的单元。 创建JUMP指令并将其插入到缺陷存储器地址之前的原始程序代码中，以绕过任何有缺陷的存储单元，而不会中断加载到存储器中的指令步骤的预期操作。 另外，JUMP指令被插入到存储器起始地址中，使处理器被迫在包含第一代码模块的第一个字节的存储器地址开始执行。 然后修改包括引用地址的某些字节码，以纠正由于插入JUMP指令而可能改变的任何地址引用，然后加载到存储器中的相应地址。

公开(公告)号：US06304127B1

公开(公告)日：2001-10-16

申请号：US09126197

申请日：1998-07-30

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G06F724

CPC classification number: H01L27/0262 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transient negative voltage pump circuit pumps the ESD voltage to a negative voltage. The negative voltage with the ESD voltage are used for early triggering of an SCR structure on the integrated circuit. In one version of the present invention, a pn junction diode of the SCR device is used as part of the negative voltage pump circuit. This saves the layout area while improving the ESD performance. The present invention improves the ESD performance of an SCR ESD protection circuit which is used for protecting the power bus or an IC pin during an ESD event.

Abstract translation: 瞬态负电压泵电路将ESD电压泵送到负电压。 具有ESD电压的负电压用于早期触发集成电路上的SCR结构。 在本发明的一个版本中，SCR装置的pn结二极管用作负电压泵电路的一部分。 这样可以节省布局面积，同时提高ESD性能。 本发明改进了用于在ESD事件期间保护电源总线或IC引脚的SCR ESD保护电路的ESD性能。

公开(公告)号：US06297686B1

公开(公告)日：2001-10-02

申请号：US09321849

申请日：1999-05-28

Applicant: Shi-Tron Lin ,  Yung-Chow Peng

Inventor： Shi-Tron Lin ,  Yung-Chow Peng

IPC: H03K301

CPC classification number: H03K19/01707 ,  H01L27/092 ,  H01L29/78609 ,  H03K19/0016

Abstract: For low-voltage and high-speed operation of a MOSFET in an integrated circuit, a small voltage is applied to a source node, causing slight forward bias of the source junction and thereby reducing its threshold voltage. Due to the combined effects of the bias at the source node and a body effect, the reduction in threshold voltage is larger than the absolute value of the source voltage being applied. A performance improvement over simply applying a bias voltage to the body (well) results. Detection of an event can be used to apply the performance boost to a critical path in the integrated circuit only when needed. Upon detection of a logic event, which determines that a signal will propagate through the critical path shortly thereafter, the source-node bias for circuit elements in the critical path can be adjusted in time for a speed improvement. However, the source remains at another potential when no signal is passing through the critical-path, to save power when not boosting speed.

Abstract translation: 对于集成电路中的MOSFET的低电压和高速操作，向源节点施加小的电压，从而导致源极结的轻微的正向偏压，从而降低其阈值电压。 由于源节点偏置和物体效应的组合效应，阈值电压的降低大于施加的源极电压的绝对值。 通过简单地将偏置电压施加到身体（井），可以提高性能。 可以使用事件的检测来仅在需要时将性能提升应用于集成电路中的关键路径。 当检测到逻辑事件确定信号在此后不久将传播通过关键路径时，关键路径中的电路元件的源节点偏置可以及时调整以提高速度。 然而，当没有信号通过关键路径时，源保持在另一个潜力，以便在不提升速度时节省功率。

公开(公告)号：US06246122B1

公开(公告)日：2001-06-12

申请号：US09345128

申请日：1999-07-06

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L2348

CPC classification number: H01L24/06 ,  H01L23/50 ,  H01L23/60 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/13034 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: An ESD protective device for protection of an integrated circuit (IC) package from electrostatic discharge damage. The ESD protective device protects the internal circuit of the IC connected to wired pins of the IC package against ESD damage due to ESD stress in neighboring no-connect pins. The ESD protective device includes an ESD protective unit coupled to the power bus and a bonding pad coupled between this ESD protective device and the no-connect pin. The ESD protective unit causes ESD stress applied to the no-connect pin to be diverted to the power bus, thus preventing ESD transfer between a no-connect pin and an active pin, which could damage the internal circuit.

Abstract translation: 一种用于保护集成电路（IC）封装免受静电放电损坏的ESD保护装置。 ESD保护装置保护连接到IC封装的有线引脚的IC的内部电路，防止由于相邻不连接引脚中的ESD应力而导致的ESD损坏。 ESD保护装置包括耦合到电源总线的ESD保护单元和耦合在该ESD保护装置和无连接引脚之间的接合焊盘。 ESD保护单元会使施加到无连接引脚的ESD应力转移到电源总线，从而防止无连接引脚和有源引脚之间的ESD传输，这可能会损坏内部电路。

公开(公告)号：US06233130B1

公开(公告)日：2001-05-15

申请号：US09126200

申请日：1998-07-30

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H02H900

CPC classification number: H01L27/0262 ,  H01L27/0251 ,  H01L29/87

Abstract: A transient voltage-pump circuit pumps the ESD voltage to a higher voltage. The pumped-high transient voltage is used for early triggering of an SCR. In one version of the present invention, a pn junction of the SCR device is used as part of the voltage-pump circuit. This saves the layout area while improving the ESD performance. The present invention improves the ESD performance of an SCR ESD protection circuit which is used for protecting the power bus or an IC pin during an ESD event.

Abstract translation: 瞬态电压泵电路将ESD电压泵送到更高的电压。 泵浦高瞬态电压用于SCR的早期触发。 在本发明的一个版本中，SCR器件的pn结用作电压 - 泵电路的一部分。 这样可以节省布局面积，同时提高ESD性能。 本发明改进了用于在ESD事件期间保护电源总线或IC引脚的SCR ESD保护电路的ESD性能。

公开(公告)号：US6107681A

公开(公告)日：2000-08-22

申请号：US45327

申请日：1998-03-20

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L23/60 ,  H01L23/48

CPC classification number: H01L23/60 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/14

Abstract: A pin-assignment method is provided for use on an IC package to arrange pin connections. The pin-assignment method can allow an improvement in the electro-static discharge (ESD) protection capability for the IC chip packed in the IC package. Specifically, the pin-assignment method organizes the no-connect pins of the IC package into groups and then assigns each of the two pins that bound each no-connect pin group to be connected to a power bus of the IC chip. This allows for an increased ESD protective capability for the no-connect pins. Moreover, the pin-assignment method can simplify the wiring complexity of the IC package.

公开(公告)号：US5959488A

公开(公告)日：1999-09-28

申请号：US12928

申请日：1998-01-24

Applicant: Shi-Tron Lin ,  Shyh-Chyi Wong

Inventor： Shi-Tron Lin ,  Shyh-Chyi Wong

IPC: H01L27/02 ,  H03K5/08

CPC classification number: H01L27/0251 ,  H01L2924/0002

Abstract: A dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor. Preferably, each MOSFET is an NMOS device. Specifically, each NMOS device includes a capacitor that is connected between the gate of the NMOS device and the pad terminal. A first resistor is connected between the gate and the p-well, while a second resistor is connected between the p-well and the grounded source. For a positive ESD pulse to VSS, the p-well is pulled up to approximately 0.7 V during the initial ESD event, such that the source junction is forward biased and that the trigger voltage of the NMOS device is lowered. At the same time, the gate voltage is coupled within the range of approximately 1 to 2 V to promote the uniform turn on of the gate fingers of the NMOS devices during the initial ESD event.

Abstract translation: 双节点电容器耦合技术用于降低触发电压并改善多指MOSFET晶体管的均匀导通。 优选地，每个MOSFET是NMOS器件。 具体地，每个NMOS器件包括连接在NMOS器件的栅极和焊盘端子之间的电容器。 第一个电阻连接在栅极和p阱之间，而第二个电阻连接在p阱和接地源之间。 对于VSS的正ESD脉冲，在初始ESD事件期间，p阱被上拉至大约0.7V，使得源极结正向偏置并且NMOS器件的触发电压降低。 同时，栅极电压耦合在大约1到2V的范围内，以促进初始ESD事件期间NMOS器件的栅极指的均匀导通。

公开(公告)号：US5742083A

公开(公告)日：1998-04-21

申请号：US778742

申请日：1997-01-02

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L27/02 ,  H01L23/62

CPC classification number: H01L27/0251 ,  H01L27/0266 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/78 ,  H01L2924/0002

Abstract: A MOSFET structure for an ESD protection circuit in a semiconductor IC device having segmented diffusion regions. The transistor includes a gate having an extended strip-shaped structure formed on the substrate of the IC device. A well region is formed in the substrate on a first side of the gate structure. A first drain diffusion region is formed in the well region, and a second drain diffusion region is formed partially inside the well region. A source diffusion region is formed in the substrate along a second side of the gate structure, opposing the first side. A field oxide layer is formed over the surface of the substrate, the field oxide layer comprises a number of finger-shaped extensions originating from the drain side of the transistor and extending into the source side of the transistor. The finger-shaped extensions divide the second drain diffusion region into a number of parallel-aligned segmented diffusion regions.

Abstract translation: 一种用于具有分段扩散区域的半导体IC器件中的ESD保护电路的MOSFET结构。 晶体管包括形成在IC器件的衬底上的延伸的带状结构的栅极。 在栅极结构的第一侧上的衬底中形成阱区。 在阱区中形成第一漏极扩散区，并且在阱区内部分地形成第二漏极扩散区。 源极扩散区沿着栅极结构的与第一侧相对的第二侧在衬底中形成。 在衬底的表面上形成场氧化物层，场氧化物层包括源自晶体管的漏极侧并延伸到晶体管的源极侧的多个指形延伸部。 指形延伸部将第二漏极扩散区域分成多个平行排列的分段扩散区域。

公开(公告)号：US5204518A

公开(公告)日：1993-04-20

申请号：US812985

申请日：1991-12-24

Applicant: Shi-Tron Lin ,  Steven A. Buhler

Inventor： Shi-Tron Lin ,  Steven A. Buhler

IPC: G01D5/26 ,  H03M1/28

CPC classification number: G01D5/26 ,  H03M1/285

Abstract: A position detector for a scanning beam comprising a plurality of rows of spaced apart sensors. Each row of sensors includes a plurality of logic zero sensors and a plurality of logic one sensors which are arranged in alternating logic order. Each row is arranged such that it is symmetrical about its center. Equal areas of logic zero sensors on each side of the center are equal distances away from the center and equal areas of logic one sensors on each side of the center are equal distances away from the center to substantially cancel out any background light effects on the sensors.

Abstract translation: 一种用于扫描光束的位置检测器，包括多行间隔开的​​传感器。 每行传感器包括多个逻辑零传感器和以交替逻辑顺序布置的多个逻辑一个传感器。 每排布置成使其相对于其中心对称。 中心每侧的逻辑零传感器的相等区域距离中心距离相等，距离相同的逻辑区域，中心两侧的一个传感器距离中心距离相等，从而基本上消除了对传感器的任何背景光影响 。

公开(公告)号：US5173602A

公开(公告)日：1992-12-22

申请号：US813173

申请日：1991-12-24

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G01B11/00 ,  G01D5/26 ,  G01D5/347

CPC classification number: G01D5/26 ,  G01D5/34792

Abstract: The present invention consists of a photocell array to determine the cross-scan position of a laser beam. The array consists of multiple rows of elongated photocells oriented perpendicular to the main scan direction of the laser beam with each row of photocells representing one bit of data. Furthermore, each row consists of alternating types of photocells, one type representing a logic 1 and the other type representing a logic 0. As the laser beam crosses this array, it energizes certain photocells on each row such that its output is a binary number that identifies the position at which the laser beam crosses the array. To improve the accuracy of the binary output, the pitch between the photocells of each row should not be reduced to less than 1/4 of the width of the laser beam. If greater accuracy is needed, the photocells should be offset while keeping the pitch between the photocells constant at a pitch not less than 1/4 of the width of the laser beam.