公开(公告)号：US10747414B2

公开(公告)日：2020-08-18

申请号：US16300028

申请日：2017-05-10

Applicant: Thinh Tran

Inventor： Thinh Tran

IPC: G06F3/0485 ,  G06Q50/00 ,  G06F16/9537 ,  G06F40/106 ,  H04L12/58

Abstract: A fluid timeline social network is provided herein. The fluid timeline social network includes a story database, an image database and a fluid timeline social network application, hosted at least partially on a server computer including a processor and a computer-readable storage medium. The fluid timeline social network application is configured to receive from a user computer device a created story, the created story including at least one of textual information and image information; receive from the user computer device a user-specified date to be associated with the created story; associate the created story with the user-specified date; associate the created story with an actual time and date that the created story is received by the fluid timeline social network application; and provide the story to the story database for storage.

公开(公告)号：US20190377778A1

公开(公告)日：2019-12-12

申请号：US16549859

申请日：2019-08-23

Applicant: Thinh Tran

Inventor： Thinh Tran

IPC: G06F17/21 ,  G06Q50/00 ,  G06F16/9537 ,  G06F3/0485 ,  G06Q10/10 ,  H04L29/08

Abstract: A fluid timeline social network is provided herein. The fluid timeline social network includes a story database, an image database and a fluid timeline social network application, hosted at least partially on a server computer including a processor and a computer-readable storage medium. The fluid timeline social network application is configured to receive from a user computer device a created story, the created story including at least one of textual information and image information; receive from the user computer device a user-specified date to be associated with the created story; associate the created story with the user-specified date; associate the created story with an actual time and date that the created story is received by the fluid timeline social network application; and provide the story to the story database for storage.

公开(公告)号：US08358557B2

公开(公告)日：2013-01-22

申请号：US13245856

申请日：2011-09-26

Applicant: Joseph Tzou ,  Thinh Tran ,  Jun Li

Inventor： Joseph Tzou ,  Thinh Tran ,  Jun Li

IPC: G11C8/00

CPC classification number: G11C8/18 ,  G11C8/12

Abstract: A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to another of the plurality of banks in synchronism with a second part of the first clock cycle, each bank having separate access circuits; and the time between consecutive accesses is faster than an access speed for back-to-back accesses to a same one of the banks; wherein during the access operations, storage locations of each bank are accessed in a same time period.

Abstract translation: 在相同时间段中多次访问存储器件的方法可以包括在第一次访问顺序中，与第一时钟周期的第一部分同步地开始对多个存储体之一的访问操作，并开始访问 与第一时钟周期的第二部分同步地操作到多个存储体中的另一个存储体，每个存储体具有单独的访问电路; 并且连续访问之间的时间比对于相同银行的背对背访问的访问速度更快; 其中在访问操作期间，在相同的时间段内访问每个存储体的存储位置。

公开(公告)号：US08040164B2

公开(公告)日：2011-10-18

申请号：US12286321

申请日：2008-09-29

Applicant: Suresh Parameswaran ,  Joseph Tzou ,  Morgan Whately ,  Thinh Tran

Inventor： Suresh Parameswaran ,  Joseph Tzou ,  Morgan Whately ,  Thinh Tran

IPC: H03B1/00 ,  H03K3/00

CPC classification number: H03K19/0005 ,  H04L25/0278

Abstract: An integrated circuit may include at least a first replica driver stage coupled between a reference impedance input and a first power supply node and having a first programmable driver impedance set by a first driver configuration value in the same manner as a first output driver section of the integrated circuit. At least a first replica input termination stage may be coupled between the reference impedance input and the first power supply node and having a first programmable termination impedance set by a first termination configuration value in the same manner as a first input termination section of the integrated circuit. An impedance programming circuit may generate at least the first driver configuration value and the first termination configuration value in response to a potential at the reference node.

Abstract translation: 集成电路可以包括至少第一复制驱动器级，其耦合在参考阻抗输入和第一电源节点之间，并且具有与第一驱动器配置值设置的第一可编程驱动器阻抗以与第一驱动器配置值的第一输出驱动器部分相同的方式 集成电路。 至少第一复制输入终端级可以耦合在参考阻抗输入和第一电源节点之间，并且具有与集成电路的第一输入终端部分相同的方式由第一终端配置值设置的第一可编程终止阻抗 。 响应于参考节点处的电位，阻抗编程电路可产生至少第一驱动器配置值和第一终端配置值。

公开(公告)号：US07719908B1

公开(公告)日：2010-05-18

申请号：US11963446

申请日：2007-12-21

Applicant: Joseph Tzou ,  Suresh Parameswaran ,  Thinh Tran

Inventor： Joseph Tzou ,  Suresh Parameswaran ,  Thinh Tran

IPC: G11C29/00

CPC classification number: G11C29/08 ,  G11C11/41 ,  G11C29/12015 ,  G11C29/50 ,  G11C29/50012

Abstract: Embodiments of the invention relate to the testing and reduction of read disturb failures in a memory, e.g., an array of SRAM cells. A read disturb test mode may be added during wafer sort to identify any marginal memory cells that may fail read disturb, thus minimizing yield loss. The read disturb test mode may include first writing data to the memory. After a predetermined time period, the read disturb test mode reads data from the same memory, and compares the read data with the data previously written to the memory. A repair signal may be generated, when the read data is different from the data previously written to the memory. Additionally, a system may be implemented to reduce read disturb failures in the memory. The system may include a match logic circuit and a data selecting circuit. When a match condition is satisfied, data is read from a register that stores the previous written data, instead of from the memory. The match logic circuit may be selectively enabled or disabled.

Abstract translation: 本发明的实施例涉及测试和减少存储器（例如SRAM单元阵列）中的读取干扰故障。 可以在晶片排序期间添加读取干扰测试模式以识别可能失败读取干扰的任何边缘存储器单元，从而使产量损失最小化。 读取干扰测试模式可以包括首先将数据写入存储器。 在预定时间段之后，读取干扰测试模式从相同存储器读取数据，并将读取的数据与先前写入存储器的数据进行比较。 当读取的数据与先前写入存储器的数据不同时，可能会产生修复信号。 此外，可以实现系统以减少存储器中的读取干扰故障。 该系统可以包括匹配逻辑电路和数据选择电路。 当满足匹配条件时，从存储先前写入数据的寄存器中读取数据，而不是从存储器读取数据。 可以选择性地启用或禁用匹配逻辑电路。

公开(公告)号：US07535772B1

公开(公告)日：2009-05-19

申请号：US10877932

申请日：2004-06-25

Applicant: Suresh Parameswaran ,  Thinh Tran

Inventor： Suresh Parameswaran ,  Thinh Tran

IPC: G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093

Abstract: Data paths (100 and 900) can be configured to accommodate two or four burst data sequences, with a data value being input/output each half clock cycle. A data sequence can be a fixed order or user-defined order depending upon a selected option. A data input path (100) can reduce power consumption with an enable signal (dinen) timed to activate after data input lines have settled values. A data output path (900) can access output data in a parallel fashion for subsequent output according to a burst sequence. Cycle latencies for such output data can include one clock cycle latency or one and a half-clock cycles. A data output path (900) can also accommodate various clocking modes, including: single clocking with a delay locked loop (DLL) type circuit enabled, single clocking with a delay locked loop (DLL) type circuit disabled, and double clocking, with a phase difference between an input clock and output clock of up to 180°.

Abstract translation: 可以将数据路径（100和900）配置为容纳两个或四个突发数据序列，其中数据值每半个时钟周期被输入/输出。 取决于所选择的选项，数据序列可以是固定顺序或用户定义的顺序。 数据输入路径（100）可以通过在数据输入线具有稳定值之后定时激活的使能信号（dinen）来降低功耗。 数据输出路径（900）可以并行地访问输出数据，以便根据突发序列进行后续输出。 这种输出数据的周期延迟可以包括一个时钟周期延迟或一个半个时钟周期。 数据输出路径（900）还可以适应各种时钟模式，包括：启用延迟锁定环路（DLL）类型电路的单一时钟，禁用延迟锁定环路（DLL）类型电路的单时钟，双时钟 输入时钟和输出时钟之间的相位差可达180°。

公开(公告)号：US20090085614A1

公开(公告)日：2009-04-02

申请号：US12286321

申请日：2008-09-29

Applicant: Suresh Parameswaran ,  Joseph Tzou ,  Morgan Whately ,  Thinh Tran

Inventor： Suresh Parameswaran ,  Joseph Tzou ,  Morgan Whately ,  Thinh Tran

IPC: H03B1/00

CPC classification number: H03K19/0005 ,  H04L25/0278

Abstract: An integrated circuit may include at least a first replica driver stage coupled between a reference impedance input and a first power supply node and having a first programmable driver impedance set by a first driver configuration value in the same manner as a first output driver section of the integrated circuit. At least a first replica input termination stage may be coupled between the reference impedance input and the first power supply node and having a first programmable termination impedance set by a first termination configuration value in the same manner as a first input termination section of the integrated circuit. An impedance programming circuit may generate at least the first driver configuration value and the first termination configuration value in response to a potential at the reference node.

Abstract translation: 集成电路可以包括至少第一复制驱动器级，其耦合在参考阻抗输入和第一电源节点之间，并且具有与第一驱动器配置值设置的第一可编程驱动器阻抗以与第一驱动器配置值的第一输出驱动器部分相同的方式 集成电路。 至少第一复制输入终止级可以耦合在参考阻抗输入和第一电源节点之间，并具有与集成电路的第一输入终端部分相同的方式由第一终端配置值设置的第一可编程终止阻抗 。 响应于参考节点处的电位，阻抗编程电路可产生至少第一驱动器配置值和第一终端配置值。