Abstract:
A release device for detaching a male plug of a cable line from a female receptacle includes a holding portion, an accommodating portion, a connecting portion and an engaging portion. The accommodating portion includes a first guiding part that is configured for alignment between the accommodating portion and the male plug. The holding portion connects to the connecting portion that connects to the accommodating portion. The accommodating portion connects to the engaging portion, which includes a concave area that is configured for engaging the male plug.
Abstract:
A control circuit and method for controlling a power converter comprises an adder, a digital compensator, and a pulse width modulation circuit. The adder acquires an output voltage difference between the output voltage and the reference output voltage. The digital compensator, which has a Z-domain transfer function, references the output voltage difference to generate a pulse width control signal with the least significant bits of the denominator coefficient in the Z-domain transfer function being regulated to achieve the load line function of the power converter. Further, the pulse modulation circuit is controlled by the pulse width control signal to generate the pulse width modulation signal to control ON/OFF of the power converter.
Abstract:
An image coding method for run-length coding (RLC), including quantizing a coefficient string representing a plurality of pixel values to generate a first quantization coefficient string, determining a cutoff quantization coefficient in the first quantization coefficient string, discarding a part of quantization coefficients of the first quantization coefficient string according to the cutoff quantization coefficient, and forming remaining quantization coefficients of the first quantization coefficient string as a second quantization coefficient string, and performing image coding to the second quantization coefficient string with the RLC.
Abstract:
An easy LSB tuning method is proposed for a digitally controlled DC-DC converter to increase the DC gain of the digitally controlled DC-DC converter under conditions of no-limit-cycle and a finite bit number to reduce steady-state error of the digitally controlled DC-DC converter. The LSB of one or more of the coefficients in the denominator of the discrete-time domain transfer function of the digital compensator in the digitally controlled DC-DC converter is so tuned that the sum of all coefficients in the denominator of the discrete-time domain transfer function becomes zero. Therefore, the influence of round-off effect on the coefficients of the digital compensator is mitigated.
Abstract:
A three-dimensional display device includes a display panel and an optical film. The display panel includes a plurality of display units arranged in a matrix. Each display unit includes a plurality of pixels configured for displaying sub-images having stereoscopic parallax. The optical film includes a plurality of lenses, each corresponding to a respective display unit. The lens is disposed opposite to the corresponding display unit and configured to split light corresponding to two sub-images of the corresponding display unit to reach both left and right viewing sides, respectively.
Abstract:
A liquid crystal display includes a pixel matrix having a plurality of pixels and a common voltage driver. Each pixel includes a TFT, a pixel electrode, and a common electrode. The pixels are defined as a first pixel group and a second pixel group. The pixels in the first pixel group all have a first polarity in each frame period, the pixels in the second pixel group all have a second polarity in each frame period, and the first polarity and the second polarity are different. The common voltage driver is configured for providing a first common voltage to the common electrodes of the pixels in the first pixel group and providing a second common voltage to the common electrodes of the pixels in the second pixel group. The first common voltage and the second common voltage are alternating voltages, and have inverse phases.
Abstract:
An exemplary fringe field switching liquid crystal display device (3) includes a first substrate (310) and a second substrate (320) disposed parallel to each other and spaced apart a predetermined distance. A liquid crystal layer (300) is interposed between the first and second substrates. A plurality of gate lines (332) and data lines (331) are formed on the second substrate, thereby defining a plurality of pixel regions. A common electrode (321) is arranged in each pixel region. And a pixel electrode (323) is arranged in each pixel region and insulated from the common electrode, the pixel electrode including a plurality of slits (350) arranged therein. The slits are separate from each other and maintain varied angles including oblique angles relative to the nearest gate lines.
Abstract:
This invention provides a paper-blocking mechanism and paper processing device using the same. The paper-blocking mechanism comprises a paper holder, a shaft connecting to a power source and driving a paper feeding portion, a restriction portion disposed on the shaft and moving between a first position and second position when the shaft is rotating, a paper blocking portion comprising a paper blocking plate and coupled to the paper processing device, wherein the restriction portion abuts the paper blocking plate to cause the paper holder in a paper blocking position when the restriction portion is in the first position, and the restriction portion doesn't abut the paper blocking plate to cause the paper holder in a paper feeding position when the restriction portion is in the second position.
Abstract:
An in plane switching liquid crystal display (IPS LCD) (100) has two substrates (110, 120) opposite to each other and spaced apart a predetermined distance; a liquid crystal layer (130) between the two substrates, and having a plurality of liquid crystal molecules; and an electrode array (111) formed on one of the substrate. Only one alignment layer (112) is provided, adjacent to the liquid crystal layer, which is formed on the substrate having the electrode array.
Abstract:
An exemplary liquid crystal display (100) includes gate lines (122), and data lines (123) cooperatively defining pixel units. Each pixel unit includes a first thin film transistor (TFT) (125), a second TFT (126), a first pixel electrode (127), and a second pixel electrode (128). Gate electrodes of the two TFTs are connected to one of the gate lines. A source electrode of the first TFT is connected to one of the data lines. A drain electrode of the first TFT is connected to the first pixel electrode. A source electrode of the second TFT is connected to the first pixel electrode. A drain electrode of the second TFT is connected to the second pixel electrode. A channel width/length ratio of the second TFT is such that a voltage of the drain electrode thereof is less than a voltage of the source electrode thereof when the second TFT is switched on.