公开(公告)号：US10331357B2

公开(公告)日：2019-06-25

申请号：US15380778

申请日：2016-12-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Betty Ann McDaniel ,  Michael D. Achenbach ,  David N. Suggs ,  Frank C. Galloway ,  Kai Troester ,  Krishnan V. Ramani

IPC: G06F3/06 ,  G06F12/0871 ,  G06F12/0897 ,  G06F9/30

Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.

公开(公告)号：US20180052613A1

公开(公告)日：2018-02-22

申请号：US15380778

申请日：2016-12-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Betty Ann McDaniel ,  Michael D. Achenbach ,  David N. Suggs ,  Frank C. Galloway ,  Kai Troester ,  Krishnan V. Ramani

IPC: G06F3/06 ,  G06F12/0871 ,  G06F12/0897

CPC classification number: G06F3/0611 ,  G06F3/0631 ,  G06F3/0643 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/30 ,  G06F12/0871 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/304 ,  G06F2212/463 ,  G06F2212/604

Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.

公开(公告)号：US09367310B2

公开(公告)日：2016-06-14

申请号：US13922340

申请日：2013-06-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Kai Troester ,  Luke Yen

IPC: G06F9/44 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838

Abstract: A processor employs a prediction table at a front end of its instruction pipeline, whereby the prediction table stores address register and offset information for store instructions; and stack offset information for stack access instructions. The stack offset information for a corresponding instruction indicates the location of the data accessed by the instruction at the processor stack relative to a base location. The processor uses pattern matching to identify predicted dependencies between load/store instructions and predicted dependencies between stack access instructions. A scheduler unit of the instruction pipeline uses the predicted dependencies to perform store-to-load forwarding or other operations that increase efficiency and reduce power consumption at the processing system.

Abstract translation: 处理器在其指令流水线的前端采用预测表，由此预测表存储用于存储指令的地址寄存器和偏移信息; 和堆栈访问指令的堆栈偏移信息。 用于相应指令的堆栈偏移信息指示由处理器堆栈处的指令相对于基本位置访问的数据的位置。 处理器使用模式匹配来识别加载/存储指令之间的预测依赖性以及堆栈访问指令之间的预测依赖性。 指令流水线的调度器单元使用预测的依赖性来执行存储到负载转发或提高处理系统的效率并降低功耗的其他操作。