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公开(公告)号：US12061919B2
公开(公告)日：2024-08-13
申请号：US18460374
申请日：2023-09-01
申请人： Dynavisor, Inc.
发明人： Sreekumar R. Nair
IPC分类号： G06F9/455 , C07K16/28 , G06F3/06 , G06F12/0868 , G06F12/1081 , G06F13/28 , A61K39/00 , G06F9/4401 , G06F12/084 , G06F12/0864
CPC分类号： G06F9/45533 , C07K16/2803 , C07K16/2887 , C07K16/2896 , G06F3/061 , G06F3/0664 , G06F3/0665 , G06F3/0685 , G06F3/0689 , G06F9/45558 , G06F12/0868 , G06F12/1081 , G06F13/28 , A61K2039/505 , A61K2039/507 , C07K2317/21 , C07K2317/24 , C07K2317/33 , C07K2317/52 , C07K2317/56 , C07K2317/565 , C07K2317/73 , C07K2317/76 , G06F3/0673 , G06F9/4411 , G06F2009/45579 , G06F12/084 , G06F12/0864 , G06F2212/152 , G06F2212/2532 , G06F2212/314 , G06F2212/463
摘要： A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.
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2.发明公开公开(公告)号：US20230289329A1
公开(公告)日：2023-09-14
申请号：US18320907
申请日：2023-05-19
申请人： Box, Inc.
发明人： Tanooj Luthra , Ritik Malhotra , Bryan Huh
IPC分类号： G06F16/182 , G06F9/46 , G06F16/23 , G06F16/172 , G06F16/185 , G06F16/188 , G06F16/17 , G06F16/174 , G06F16/176 , G06F16/957 , H04L67/00 , G06F12/1081 , H04L65/70 , H04L65/75 , H04L9/40 , H04L67/1097 , G06F12/0891 , G06F12/122 , H04L67/06 , H04N19/40 , H04L65/80 , G06F16/242 , G06F16/22 , G06F16/11
CPC分类号： G06F16/182 , G06F9/46 , G06F16/23 , G06F16/172 , G06F16/183 , G06F16/185 , G06F16/188 , G06F16/1727 , G06F16/1748 , G06F16/1774 , G06F16/9574 , H04L67/34 , G06F12/1081 , H04L65/70 , H04L65/762 , H04L63/0428 , H04L67/1097 , G06F12/0891 , G06F12/122 , H04L67/06 , H04N19/40 , H04L65/80 , G06F16/2443 , G06F16/22 , G06F16/196 , G06F16/113 , G06F2212/1016 , G06F2212/463 , G06F2212/657 , G06F2212/1044 , G06F2212/154 , G06F2212/60
摘要： Systems, methods and computer program products for high-performance, low latency start-up of large shared media files. A method for low latency startup with low defect playback commences upon identifying a first media file having a first format to be converted to a second media file having a second format. A scheduler divides the first media file into multiple partitions separated by partition boundaries. The method continues by converting the partitions into respective converted partitions that comport with the second format. Determinations as to the position of the partition boundaries is made based on measurable conditions present at a particular moment in time. Different formats receive different treatment based on the combination of characteristics of the first format, characteristics of the second format, as well as on characteristics of measurable conditions present at the moment in time just before conversion of a segment.
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公开(公告)号：US20180150309A1
公开(公告)日：2018-05-31
申请号：US15880092
申请日：2018-01-25
申请人： Dynavisor, Inc.
发明人： Sreekumar Nair
IPC分类号： G06F9/455 , G06F12/0868 , G06F3/06 , G06F12/1081 , G06F13/28 , G06F9/4401 , G06F12/084 , G06F12/0864
CPC分类号： G06F9/45533 , G06F3/061 , G06F3/0664 , G06F3/0665 , G06F3/0685 , G06F3/0689 , G06F9/4411 , G06F9/45558 , G06F12/084 , G06F12/0864 , G06F12/0868 , G06F12/1081 , G06F13/28 , G06F2003/0692 , G06F2009/45579 , G06F2212/152 , G06F2212/2532 , G06F2212/314 , G06F2212/463
摘要： A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.
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公开(公告)号：US09940240B2
公开(公告)日：2018-04-10
申请号：US14514412
申请日：2014-10-15
IPC分类号： G06F15/167 , G06F12/0866
CPC分类号： G06F12/0866 , G06F2212/224 , G06F2212/461 , G06F2212/463 , Y02D10/13
摘要： A persistent caching system is provided. The persistent caching system includes a storage system having a caching server for storing data, and a client for accessing the data through a network. The caching server is configured to store the data in a number of virtual memory blocks. The virtual memory blocks refer to an associated memory-mapped file in a file system of the caching server. The caching server is configured to export addresses of the virtual memory blocks to the client. The client is configured to access at least some of the virtual memory blocks through RDMA using the exported addresses. The caching server is configured to page virtual memory blocks being accessed by one or more clients through RDMA to and/or from the memory-mapped files associated with the accessed virtual memory blocks.
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公开(公告)号：US20180052613A1
公开(公告)日：2018-02-22
申请号：US15380778
申请日：2016-12-15
发明人： Betty Ann McDaniel , Michael D. Achenbach , David N. Suggs , Frank C. Galloway , Kai Troester , Krishnan V. Ramani
IPC分类号： G06F3/06 , G06F12/0871 , G06F12/0897
CPC分类号： G06F3/0611 , G06F3/0631 , G06F3/0643 , G06F3/0659 , G06F3/0673 , G06F9/30 , G06F12/0871 , G06F12/0897 , G06F2212/1024 , G06F2212/304 , G06F2212/463 , G06F2212/604
摘要： A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.
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公开(公告)号：US09875192B1
公开(公告)日：2018-01-23
申请号：US14750973
申请日：2015-06-25
IPC分类号： G06F12/12 , G06F12/122 , G06F9/455 , G06F9/50 , G06F9/30 , G06F17/30 , G06F12/0871
CPC分类号： G06F12/122 , G06F9/45558 , G06F9/50 , G06F12/0871 , G06F17/30088 , G06F2009/45583 , G06F2212/1016 , G06F2212/152 , G06F2212/455 , G06F2212/463 , G06F2212/604 , G06F2212/69
摘要： A system and method that includes receiving a call, from a thread, of a plurality of threads performing the same operations in parallel, in association with a virtual machine, to read a block of data from a file, allocating memory accessible by both the virtual machine and the plurality of threads for receiving the block, and providing the block by causing the block to be copied from the file associated with a file descriptor into the memory. A system and method that includes receiving a call from a thread of a plurality of threads executing the same instructions in parallel in association with a virtual machine, to write a block of data to a file, configuring a buffer accessible by the virtual machine to receive the block, writing the block to the configured buffer, and causing the block to be copied from the configured buffer to the file.
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7.发明授权公开(公告)号：US09852072B2
公开(公告)日：2017-12-26
申请号：US14790701
申请日：2015-07-02
申请人： NetApp, Inc.
发明人： Priya Sehgal , Sourav Basu
IPC分类号： G06F12/0815 , G06F12/0813 , H04L29/08
CPC分类号： G06F12/0815 , G06F11/1446 , G06F12/0804 , G06F12/0813 , G06F12/0868 , G06F2212/1016 , G06F2212/154 , G06F2212/314 , G06F2212/463 , G06F2212/466 , G06F2212/621 , H04L67/2842
摘要： A method, non-transitory computer readable medium, and device that assists with file-based host-side caching and application consistent write back includes receiving a write operation on a file from a client computing device. When the file for which the write operation has been received is determined when the file is present in the cache. An acknowledgement is sent back to the client computing device indicating the acceptance of the write operation when the file for which the write operation has been received is determined to be present within the cache. The write-back operation is completed for data present in the cache of the storage management computing device to one of the plurality of servers upon sending the acknowledgement.
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公开(公告)号：US09734118B2
公开(公告)日：2017-08-15
申请号：US14515330
申请日：2014-10-15
发明人： Eunbae Yoon , Pai H. Chou
IPC分类号： G06F3/00 , G06F13/00 , G06F13/14 , G06F13/42 , G06F13/28 , G06F13/16 , G06F12/02 , G06F11/34 , G06F12/0868 , G06F13/38 , G06F12/0804
CPC分类号： G06F13/4282 , G06F11/3476 , G06F12/0238 , G06F12/0246 , G06F12/0804 , G06F12/0868 , G06F13/1673 , G06F13/287 , G06F13/385 , G06F2212/214 , G06F2212/222 , G06F2212/463 , G06F2212/466 , G06F2212/62 , G06F2212/7203 , G06F2212/7208 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A new serial bus interface module that enables constrained sensor systems to better match flash-based storage devices' (SD card) read and write performance. The serial bus interface module augments existing flash-based storage with non-volatile random-access memory to form a hybrid storage system using the most popularly used master-slave bus architecture. Together with PSC-like features, the serial bus interface module not only enables slave-to-slave transfer (therefore eliminating the double-transaction problem) but also reads caching (one source to multi-sink) and buffering while flushing. These transaction types enable multi-sector write for significantly faster speed and lower energy overhead, while the use of non-volatile memory for metadata caching means low risk of file-system corruption in the event of power failure. The serial bus interface also enables the direct data transfer from sensors to storage or communication modules without requiring the microprocessor's intervention.
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公开(公告)号：US09710481B1
公开(公告)日：2017-07-18
申请号：US14498708
申请日：2014-09-26
CPC分类号： G06F17/30218 , G06F12/0246 , G06F12/0868 , G06F12/121 , G06F2212/1016 , G06F2212/154 , G06F2212/161 , G06F2212/222 , G06F2212/311 , G06F2212/452 , G06F2212/463 , G06F2212/7202
摘要： A virtual installation module running on a user device determines that at least one application file chunk is to be stored in a memory of the user device prior to being executed, wherein the application file chunk includes a subset of the data of the application and is stored on a remote storage device that correspond to an application to be executed by the processing device. The virtual installation module determines when a request to execute the application on the user device will be received and stores the at least one application file chunk from the remote storage device in the memory of the user device based at least in part on when the at least one application file chunk will be utilized during execution of the application.
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10.发明申请公开(公告)号：US20170097897A1
公开(公告)日：2017-04-06
申请号：US15258215
申请日：2016-09-07
发明人： Hideyuki SAITO
IPC分类号： G06F12/1009
CPC分类号： G06F12/0873 , G06F12/0246 , G06F2212/1021 , G06F2212/463 , G06F2212/657 , G06F2212/7201
摘要： Disclosed herein is an information processing device including a host unit adapted to request data access by specifying a logical address of a secondary storage device, and a controller adapted to accept the data access request and convert the logical address into a physical address using an address conversion table to perform data access to an associated area of the secondary storage device, in which an address space defined by the address conversion table includes a coarsely granular address space that collectively associates, with logical addresses, physical addresses that are in units larger than those in which data is read.
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