公开(公告)号：US20190196974A1

公开(公告)日：2019-06-27

申请号：US15855838

申请日：2017-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Ganesh Balakrishnan ,  Ravindra N. Bhargava

IPC: G06F12/0897 ,  G06F12/121

Abstract: Systems, apparatuses, and methods for implementing a tag accelerator cache are disclosed. A system includes at least a data cache and a control unit coupled to the data cache via a memory controller. The control unit includes a tag accelerator cache (TAC) for caching tag blocks fetched from the data cache. The data cache is organized such that multiple tags are retrieved in a single access. This allows hiding the tag latency penalty for future accesses to neighboring tags and improves cache bandwidth. When a tag block is fetched from the data cache, the tag block is cached in the TAC. Memory requests received by the control unit first lookup the TAC before being forwarded to the data cache. Due to the presence of spatial locality in applications, the TAC can filter out a large percentage of tag accesses to the data cache, resulting in latency and bandwidth savings.

公开(公告)号：US20190188137A1

公开(公告)日：2019-06-20

申请号：US15846008

申请日：2017-12-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Amit P. Apte ,  Ganesh Balakrishnan ,  Eric Christopher Morton ,  Elizabeth M. Cooper ,  Ravindra N. Bhargava

IPC: G06F12/0817 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0871

CPC classification number: G06F12/0817 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0871 ,  G06F12/128 ,  G06F2212/283 ,  G06F2212/604 ,  G06F2212/621

Abstract: Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.

公开(公告)号：US20190179758A1

公开(公告)日：2019-06-13

申请号：US15839662

申请日：2017-12-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Amit P. Apte ,  Ganesh Balakrishnan ,  Ann Ling ,  Ravindra N. Bhargava

IPC: G06F12/0862 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0831

Abstract: Systems, apparatuses, and methods for accelerating cache to cache data transfers are disclosed. A system includes at least a plurality of processing nodes and prediction units, an interconnect fabric, and a memory. A first prediction unit is configured to receive memory requests generated by a first processing node as the requests traverse the interconnect fabric on the path to memory. When the first prediction unit receives a memory request, the first prediction unit generates a prediction of whether data targeted by the request is cached by another processing node. The first prediction unit is configured to cause a speculative probe to be sent to a second processing node responsive to predicting that the data targeted by the memory request is cached by the second processing node. The speculative probe accelerates the retrieval of the data from the second processing node if the prediction is correct.

公开(公告)号：US20140365729A1

公开(公告)日：2014-12-11

申请号：US13912809

申请日：2013-06-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Marius Evers ,  John Kalamatianos ,  Carl D. Dietz ,  Richard E. Klass ,  Ravindra N. Bhargava

IPC: G06F12/08

CPC classification number: G06F12/0855 ,  G06F12/0844 ,  G06F12/0846

Abstract: The present application describes embodiments of techniques for picking a data array lookup request for execution in a data array pipeline a variable number of cycles behind a corresponding tag array lookup request that is concurrently executing in a tag array pipeline. Some embodiments of a method for picking the data array lookup request include picking the data array lookup request for execution in a data array pipeline of a cache concurrently with execution of a tag array lookup request in a tag array pipeline of the cache. The data array lookup request is picked for execution in response to resources of the data array pipeline becoming available after picking the tag array lookup request for execution. Some embodiments of the method may be implemented in a cache.

Abstract translation: 本申请描述了用于在数据阵列流水线中选择用于执行数据阵列查找请求的技术的实施例，该数据阵列查找请求在标签阵列管线中同时执行的对应的标签数组查找请求后面的可变数量的循环。 用于选择数据阵列查找请求的方法的一些实施例包括在高速缓存的标签阵列管线中执行标签阵列查找请求的同时，在高速缓存的数据阵列流水线中选择用于执行的数据阵列查找请求。 选择数据数组查找请求以在执行标签数组查找请求之后响应于数据数组流水线变得可用的资源进行执行。 该方法的一些实施例可以在高速缓存中实现。