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    Debug Trace of Cache Memory Requests
    21.
    发明申请
    Debug Trace of Cache Memory Requests 有权

    公开(公告)号：US20230061419A1

    公开(公告)日：2023-03-02

    申请号：US17538939

    申请日：2021-11-30

    Applicant: Apple Inc.

    Inventor： Andrew J. Beaumont-Smith ,  Sandeep Gupta ,  Krishna C. Potnuru ,  Matthias Knoth

    IPC: G06F11/34 ,  G06F12/02 ,  G06F11/30

    Abstract: An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.

    Cache way prediction
    22.
    发明授权
    Cache way prediction 有权

    公开(公告)号：US10157137B1

    公开(公告)日：2018-12-18

    申请号：US14861470

    申请日：2015-09-22

    Applicant: Apple Inc.

    Inventor： Prashant Jain ,  Jason M. Kassoff ,  Sandeep Gupta

    IPC: G06F12/08 ,  G06F12/0864 ,  G06F3/06

    Abstract: Techniques are disclosed relating to set-associative caches in processors. In one embodiment, an integrated circuit is disclosed that includes a set-associative cache configured to receive a request for a data block stored in one of a plurality of ways within the cache, the request specifying an address, a portion of which is a tag value. In such an embodiment, the integrated circuit includes a way prediction circuit configured to predict, based on the tag value, a way in which the requested data block is stored. The integrated circuit further includes a tag array circuit configured to perform a comparison of a portion of the tag value with a set of previously stored tag portions corresponding to the plurality of ways. The tag array circuit is further configured to determine whether the request hits in the cache based on the predicted way and an output of the comparison.

    Multi-core processor instruction throttling
    23.
    发明授权
    Multi-core processor instruction throttling 有权
    多核处理器指令调节

    公开(公告)号：US09383806B2

    公开(公告)日：2016-07-05

    申请号：US13864723

    申请日：2013-04-17

    Applicant: Apple Inc.

    Inventor： Wei-Han Lien ,  Gerard R Williams, III ,  Rohit Kumar ,  Sandeep Gupta ,  Suresh Periyacheri ,  Shih-Chieh R Wen

    IPC: G06F1/32

    CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172

    Abstract: An apparatus for performing instruction throttling for a multi-processor system is disclosed. The apparatus may include a power estimation circuit, a table, a comparator, and a finite state machine. The power estimation circuit may be configured to receive information on high power instructions issued to a first processor and a second processor, and generate a power estimate dependent upon the received information. The table may be configured to store one or more pre-determined power threshold values, and the comparator may be configured to compare the power estimate with at least one of the pre-determined power threshold values. The finite state machine may be configured to adjust the throttle level of the first and second processors dependent upon the result of the comparison.

    Abstract translation: 公开了一种用于执行多处理器系统的指令调节的装置。 该装置可以包括功率估计电路，表，比较器和有限状态机。 功率估计电路可以被配置为接收关于发给第一处理器和第二处理器的高功率指令的信息，并且根据所接收的信息生成功率估计。 该表可以被配置为存储一个或多个预定功率阈值，并且比较器可以被配置为将功率估计与预定功率阈值中的至少一个进行比较。 有限状态机可以被配置为根据比较的结果来调节第一和第二处理器的节气门位置。

    REDUCING LATENCY FOR POINTER CHASING LOADS
    24.
    发明申请
    REDUCING LATENCY FOR POINTER CHASING LOADS 有权
    减少点火负荷的延迟

    公开(公告)号：US20150309792A1

    公开(公告)日：2015-10-29

    申请号：US14264789

    申请日：2014-04-29

    Applicant: Apple Inc.

    Inventor： Stephan G. Meier ,  Pradeep Kanapathipillai ,  Sandeep Gupta

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30043 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3861

    Abstract: Systems, methods, and apparatuses for reducing the load to load/store address latency in an out-of-order processor. When a producer load is detected in the processor pipeline, the processor predicts whether the producer load is going to hit in the store queue. If the producer load is predicted not to hit in the store queue, then a dependent load or store can be issued early. The result data of the producer load is then bypassed forward from the data cache directly to the address generation unit. This result data is then used to generate an address for the dependent load or store, reducing the latency of the dependent load or store by one clock cycle.

    Abstract translation: 用于减少在乱序处理器中加载/存储地址延迟的负载的系统，方法和装置。 当在处理器流水线中检测到生产者负载时，处理器预测生产者负载是否要在存储队列中命中。 如果生产者负载被预测不会在商店队列中击中，则可以提前发出依赖负载或商店。 然后，生成器负载的结果数据从数据高速缓存直接旁路到地址生成单元。 然后，该结果数据用于生成相关负载或存储的地址，从而将依赖负载或存储的延迟减少一个时钟周期。

    Debug Trace of Cache Memory Requests
    26.
    发明公开
    Debug Trace of Cache Memory Requests 审中-公开

    公开(公告)号：US20230418724A1

    公开(公告)日：2023-12-28

    申请号：US18344170

    申请日：2023-06-29

    Applicant: Apple Inc.

    Inventor： Andrew J. Beaumont-Smith ,  Sandeep Gupta ,  Krishna C. Potnuru ,  Matthias Knoth

    IPC: G06F11/34 ,  G06F11/30 ,  G06F12/02

    CPC classification number: G06F11/348 ,  G06F11/3037 ,  G06F12/0223 ,  G06F2212/1008

    Abstract: An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.

    Request Ordering in a Cache
    27.
    发明公开
    Request Ordering in a Cache 审中-公开

    公开(公告)号：US20230359557A1

    公开(公告)日：2023-11-09

    申请号：US18353830

    申请日：2023-07-17

    Applicant: Apple Inc.

    Inventor： Sandeep Gupta ,  Brian P. Lilly ,  Krishna C. Potnuru

    IPC: G06F12/0802

    CPC classification number: G06F12/0802 ,  G06F2212/60

    Abstract: A cache may include multiple request handling pipes, each of which may further include multiple request buffers, for storing device requests from one or more processors to one or more devices. Some of the device requests may require to be sent to the devices according to an order. For a given one of such device requests, the cache may select a request handling pipe, based on an address indicated by the device request, and select a request buffer, based on the available entries of the request buffers of the selected request handling pipe, to store the device request. The cache may further use a first-level and a second-level token stores to track and maintain the device requests in order when transmitting the device requests to the devices.

    Request ordering in a cache
    28.
    发明授权
    Request ordering in a cache 有权

    公开(公告)号：US11741009B1

    公开(公告)日：2023-08-29

    申请号：US17526944

    申请日：2021-11-15

    Applicant: Apple Inc.

    Inventor： Sandeep Gupta ,  Brian P Lilly ,  Krishna C Potnuru

    IPC: G06F12/00 ,  G06F12/0802

    CPC classification number: G06F12/0802 ,  G06F2212/60

    Abstract: A cache may include multiple request handling pipes, each of which may further include multiple request buffers, for storing device requests from one or more processors to one or more devices. Some of the device requests may require to be sent to the devices according to an order. For a given one of such device requests, the cache may select a request handling pipe, based on an address indicated by the device request, and select a request buffer, based on the available entries of the request buffers of the selected request handling pipe, to store the device request. The cache may further use a first-level and a second-level token stores to track and maintain the device requests in order when transmitting the device requests to the devices.

    Debug trace of cache memory requests
    29.
    发明授权
    Debug trace of cache memory requests 有权

    公开(公告)号：US11740993B2

    公开(公告)日：2023-08-29

    申请号：US17538939

    申请日：2021-11-30

    Applicant: Apple Inc.

    Inventor： Andrew J. Beaumont-Smith ,  Sandeep Gupta ,  Krishna C. Potnuru ,  Matthias Knoth

    IPC: G06F12/00 ,  G06F11/34 ,  G06F11/30 ,  G06F12/02

    CPC classification number: G06F11/348 ,  G06F11/3037 ,  G06F12/0223 ,  G06F2212/1008

    Abstract: An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.

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