中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

25 records (took 0.014 seconds)

    Bitline write assist circuitry
    22.
    发明授权
    Bitline write assist circuitry 有权

    公开(公告)号：US10217496B1

    公开(公告)日：2019-02-26

    申请号：US15907951

    申请日：2018-02-28

    Applicant: Arm Limited

    Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Satinderjit Singh ,  Shri Sagar Dwivedi ,  Bo Zheng ,  Fakhruddin Ali Bohra

    IPC: G11C7/00 ,  G11C7/12 ,  G11C7/10 ,  G11C11/4097 ,  G11C11/419

    Abstract: Various implementations described herein are directed to an integrated circuit with memory circuitry having an array of bitcells that are accessible via multiple bitlines. The integrated circuit may include a write driver coupled to at least one bitline of the multiple bitlines through a column multiplexer. The integrated circuit may include a pass transistor coupled to the write driver and the column multiplexer via a write data line. The integrated circuit may include a charge storage device coupled between the pass transistor and write assist enable circuitry. The integrated circuit may include a transmission gate coupled to a gate of the write driver. The integrated circuit may include a clamp transistor coupled between the gate of write driver and the charge storage device such that the clamp transistor receives a voltage assist signal from the charge storage device at the gate of the write driver.

    Memory circuitry with write assist
    24.
    发明授权
    Memory circuitry with write assist 有权
    具有写入辅助功能的存储器电路

    公开(公告)号：US09070431B2

    公开(公告)日：2015-06-30

    申请号：US14063612

    申请日：2013-10-25

    Applicant: ARM LIMITED

    Inventor： Frank Guo ,  Martin Jay Kinkade ,  Bo Zheng ,  Brian Reed ,  Shrisagar Dwivedi

    IPC: G11C7/10 ,  G11C7/12

    CPC classification number: G11C7/12 ,  G11C7/222 ,  G11C11/419

    Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.

    Abstract translation: 存储器电路具有用于在写入操作期间产生较低电源电压的写辅助电路。 写辅助电路包括多个串联连接的交换机，包括头部交换机和页脚开关。 标题偏置电路产生标题偏置电压，页脚偏置电路产生页脚偏置电压。 标头偏置电压是具有在电源电压电平和接地电压电平之间的电压电平的模拟信号。 页脚偏置电压是一个模拟信号，其电压电平介于电源电压电平和接地电压电平之间。 在写操作期间，要写入的目标比特单元通过头部开关经由电流路径被提供，同时它们分别由头部偏置电压和页脚偏置电压控制。

    Integrated level shifting latch circuit and method of operation of such a latch circuit
    25.
    发明授权
    Integrated level shifting latch circuit and method of operation of such a latch circuit 有权
    集成电平转换锁存电路和这种锁存电路的操作方法

    公开(公告)号：US09069652B2

    公开(公告)日：2015-06-30

    申请号：US13782077

    申请日：2013-03-01

    Applicant: ARM LIMITED

    Inventor： Gus Yeung ,  Bo Zheng ,  Frank Guo

    IPC: G11C7/00 ,  G06F12/00 ,  G11C5/14 ,  G11C11/417 ,  G11C7/10

    CPC classification number: G06F12/00 ,  G11C5/147 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1084 ,  G11C7/1087 ,  G11C11/417

    Abstract: An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry.

    Abstract translation: 集成电平移位锁存电路接收第一电压域中的输入信号并在第二电压域中产生输出信号。 数据保持电路在透明阶段工作，其中数据值经受电平移位功能，并根据输入信号写入数据保持电路。 控制电路控制数据保持电路在时钟信号的第一阶段期间在透明阶段中工作，并且在时钟信号的第二阶段期间操作在锁存阶段。 写入电路将数据值写入数据保持电路。 竞争缓解电路在透明阶段期间减少数据保持电路内的至少一个组件的压降。

Patent Agency Ranking