公开(公告)号：US12066855B2

公开(公告)日：2024-08-20

申请号：US18091719

申请日：2022-12-30

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Akash Bangalore Srinivasa ,  Munish Kumar ,  Khushal Gelda ,  Akshay Kumar

IPC: G06F1/00 ,  G06F1/06 ,  G06F1/10 ,  G06F11/30

CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F11/3062

Abstract: Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.

公开(公告)号：US20180331681A1

公开(公告)日：2018-11-15

申请号：US16042949

申请日：2018-07-23

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Vivek Nautiyal ,  Andy Wangkun Chen ,  Jitendra Dasani ,  Bo Zheng ,  Akshay Kumar ,  Vivek Asthana

IPC: H03K17/22 ,  G11C5/14

CPC classification number: H03K17/223 ,  G11C5/148

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

公开(公告)号：US10033376B2

公开(公告)日：2018-07-24

申请号：US15143197

申请日：2016-04-29

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Vivek Nautiyal ,  Andy Wangkun Chen ,  Jitendra Dasani ,  Bo Zheng ,  Akshay Kumar ,  Vivek Asthana

IPC: H03L7/00 ,  H03K17/22 ,  G11C5/14

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

公开(公告)号：US11081156B2

公开(公告)日：2021-08-03

申请号：US16504072

申请日：2019-07-05

Applicant: Arm Limited

Inventor： Surya Prakash Gupta ,  El Mehdi Boujamaa ,  Cyrille Nicolas Dray ,  Piyush Jain ,  Akshay Kumar

IPC: G11C11/16

Abstract: Various implementations described herein are directed to device having a clock generator that provides write reference signals. The device may include a voltage divider that receives the write reference signals and provides an output reference signal based on write polarity of the write reference signals. The device may include a voltage regulator that receives the output reference signal and provides a regulated voltage to a load based on the output reference signal.

公开(公告)号：US10217743B2

公开(公告)日：2019-02-26

申请号：US15434659

申请日：2017-02-16

Applicant: ARM Limited

Inventor： Akshay Kumar ,  Saikat Kumar Banik

IPC: G11C11/00 ,  H01L27/092 ,  G11C29/00 ,  G11C5/02 ,  G11C11/417

Abstract: Various implementations described herein are directed to an integrated circuit having a memory cell array disposed in a first area of the integrated circuit. The memory cell array may include memory cells with first transistors of multiple types. The integrated circuit may include a process sensor disposed in a second area of the integrated circuit that is different than the first area. The process sensor may include a process detector having second transistors of the multiple types that are separate from the first transistors. The second transistors of the process detector may be arranged for detecting process variation of the memory cells of the memory cell array.

公开(公告)号：US20240219955A1

公开(公告)日：2024-07-04

申请号：US18091719

申请日：2022-12-30

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Akash Bangalore Srinivasa ,  Munish Kumar ,  Khushal Gelda ,  Akshay Kumar

IPC: G06F1/10 ,  G06F1/06 ,  G06F11/30

CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F11/3062

Abstract: Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.

公开(公告)号：US20200075095A1

公开(公告)日：2020-03-05

申请号：US16466149

申请日：2017-11-10

Applicant: Arm Limited

Inventor： Akshay Kumar

IPC: G11C13/00

Abstract: Broadly speaking, embodiments of the present techniques provide apparatus and methods for generating a reference current for a memory array sensing scheme, and for using the generated reference current to sense the state of memory cells within the memory array. The generated reference current is particularly suitable for distinguishing between a high resistance state and a low resistance state.

公开(公告)号：US10425076B2

公开(公告)日：2019-09-24

申请号：US16042949

申请日：2018-07-23

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Vivek Nautiyal ,  Andy Wangkun Chen ,  Jitendra Dasani ,  Bo Zheng ,  Akshay Kumar ,  Vivek Asthana

IPC: H03K17/22 ,  G11C5/14

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

公开(公告)号：US09882576B1

公开(公告)日：2018-01-30

申请号：US15398142

申请日：2017-01-04

Applicant: ARM Limited

Inventor： Bal S. Sandhu ,  Piyush Agarwal ,  Akshay Kumar

IPC: H03M1/78 ,  H03M1/12 ,  H03M1/38

CPC classification number: H03M1/1004 ,  H03M1/46 ,  H03M1/785

Abstract: An analog-to-digital converter (ADC) and method of operation thereof are provided for converting an analog signal to a digital signal. The ADC utilizes Correlated Electron Material (CEM) devices that may contain a transition metal oxide (TMO), such as Nickel Oxide (NiO). The ADC may include an interconnect circuit that is operable to couple a power supply to the CEM devices. The power supply is controlled to program the resistance of the CEM devices and thereby control performance characteristics of the ADC.

公开(公告)号：US20170317672A1

公开(公告)日：2017-11-02

申请号：US15143197

申请日：2016-04-29

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Vivek Nautiyal ,  Andy Wangkun Chen ,  Jitendra Dasani ,  Bo Zheng ,  Akshay Kumar ,  Vivek Asthana

IPC: H03K17/22 ,  G11C5/14

CPC classification number: H03K17/223 ,  G11C5/148

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.