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    Read and Write Access Techniques
    2.
    发明申请
    Read and Write Access Techniques 有权

    公开(公告)号：US20210098032A1

    公开(公告)日：2021-04-01

    申请号：US16584898

    申请日：2019-09-26

    Applicant: Arm Limited

    Inventor： Lalit Gupta ,  Bo Zheng ,  El Mehdi Boujamaa ,  Fakhruddin Ali Bohra

    IPC: G11C7/10 ,  G11C11/419 ,  G11C11/16 ,  G11C11/418

    Abstract: Various implementations described herein refer to a method for providing single port memory with multiple different banks having a first bank and a second bank that is different than the first bank. The method may include coupling multiple wordlines to the single port memory including coupling a first wordline to the first bank and coupling a second wordline to the second bank. The method may include performing multiple memory access operations concurrently in the single port memory.

    Memory Circuitry Using Write Assist Voltage Boost
    3.
    发明申请
    Memory Circuitry Using Write Assist Voltage Boost 有权
    使用写辅助电压提升的存储电路

    公开(公告)号：US20160005448A1

    公开(公告)日：2016-01-07

    申请号：US14857527

    申请日：2015-09-17

    Applicant: ARM Limited

    Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Gus Yeung ,  Bo Zheng ,  George Lattimore

    IPC: G11C8/12 ,  G11C8/18 ,  G11C7/22

    CPC classification number: G11C8/12 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

    Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

    Abstract translation: 在包括位单元6的阵列4的存储器2中，写入驱动器电路14使用在写入操作期间被提升到低于正常电平的升压写入信号。 列选择晶体管16由列选择电路12驱动。当列被选择时，列选择信号被提升到低于正常水平，并且当选择列时升高到高于正常水平。 在列选择电路12内采用电压升压电路，例如电荷泵20,22，以实现列选择信号的这些提升电平。

    Memory device and method of controlling leakage current within such a memory device
    4.
    发明授权
    Memory device and method of controlling leakage current within such a memory device 有权
    存储器件和控制这种存储器件内的漏电流的方法

    公开(公告)号：US09171634B2

    公开(公告)日：2015-10-27

    申请号：US13827815

    申请日：2013-03-14

    Applicant: ARM LIMITED

    Inventor： Bo Zheng ,  Gus Yeung ,  Fakhruddin ali Bohra

    IPC: G11C16/28 ,  G11C7/12 ,  G11C8/08 ,  G11C11/418 ,  G11C11/419

    CPC classification number: G11C16/28 ,  G11C7/12 ,  G11C8/08 ,  G11C11/418 ,  G11C11/419

    Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column has an active mode of operation where a read operation may be performed on an activated memory cell within that column group, and a non-active mode of operation where the read operation is not performable. Precharge circuitry is used, for each column group, to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell includes coupling circuitry connected between the associated read bit line and a reference line associated with the column group containing that memory cell.

    Abstract translation: 存储器装置包括布置成多个行和列的存储器单元的阵列，每行耦合到相关联的读取字线，并且每列形成至少一个列组，其中每个列组的存储单元耦合到 相关的读位线。 每列具有主动操作模式，其中可以对该列组内的激活的存储器单元执行读取操作，以及读操作不可执行的非活动操作模式。 对于每个列组，预充电电路用于在读取操作之前将相关联的读取位线预充电到第一电压电平。 每个存储单元包括连接在相关读取位线和与包含该存储器单元的列组相关联的参考线之间的耦合电路。

    Memory circuitry using write assist voltage boost
    8.
    发明授权
    Memory circuitry using write assist voltage boost 有权
    使用写辅助电压提升的存储电路

    公开(公告)号：US09142266B2

    公开(公告)日：2015-09-22

    申请号：US14083619

    申请日：2013-11-19

    Applicant: ARM LIMITED

    Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Gus Yeung ,  Bo Zheng ,  George Lattimore

    IPC: G11C7/00 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C7/22 ,  G11C5/14

    CPC classification number: G11C8/12 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

    Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

    Abstract translation: 在包括位单元6的阵列4的存储器2中，写入驱动器电路14使用在写入操作期间被提升到低于正常电平的升压写入信号。 列选择晶体管16由列选择电路12驱动。当列被选择时，列选择信号被提升到低于正常水平，并且当选择列时升高到高于正常水平。 在列选择电路12内采用电压升压电路，例如电荷泵20,22，以实现列选择信号的这些提升电平。

    MEMORY CIRCUITRY USING WRITE ASSIST VOLTAGE BOOST
    9.
    发明申请
    MEMORY CIRCUITRY USING WRITE ASSIST VOLTAGE BOOST 有权
    使用写辅助电压升压的存储器电路

    公开(公告)号：US20150138901A1

    公开(公告)日：2015-05-21

    申请号：US14083619

    申请日：2013-11-19

    Applicant: Arm Limited

    Inventor： Andy Wangkun CHEN ,  Yew Keong Chong ,  Gus Yeung ,  Bo Zheng ,  George Lattimore

    IPC: G11C7/12 ,  G11C8/12

    CPC classification number: G11C8/12 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

    Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

    Abstract translation: 在包括位单元6的阵列4的存储器2中，写入驱动器电路14使用在写入操作期间被提升到低于正常电平的升压写入信号。 列选择晶体管16由列选择电路12驱动。当列被选择时，列选择信号被提升到低于正常水平，并且当选择列时升高到高于正常水平。 在列选择电路12内采用电压升压电路，例如电荷泵20,22，以实现列选择信号的这些提升电平。

    MEMORY CIRCUITRY WITH WRITE ASSIST
    10.
    发明申请
    MEMORY CIRCUITRY WITH WRITE ASSIST 有权
    存储器电路与写协助

    公开(公告)号：US20150117119A1

    公开(公告)日：2015-04-30

    申请号：US14063612

    申请日：2013-10-25

    Applicant: ARM LIMITED

    Inventor： Frank GUO ,  Martin Jay Kinkade ,  Bo Zheng ,  Brian Reed ,  Shrisagar Dwivedi

    IPC: G11C7/12

    CPC classification number: G11C7/12 ,  G11C7/222 ,  G11C11/419

    Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.

    Abstract translation: 存储器电路具有用于在写入操作期间产生较低电源电压的写辅助电路。 写辅助电路包括多个串联连接的交换机，包括头部交换机和页脚开关。 标题偏置电路产生标题偏置电压，页脚偏置电路产生页脚偏置电压。 标头偏置电压是具有在电源电压电平和接地电压电平之间的电压电平的模拟信号。 页脚偏置电压是一个模拟信号，其电压电平介于电源电压电平和接地电压电平之间。 在写操作期间，要写入的目标比特单元通过头部开关经由电流路径被提供，同时它们分别由头部偏置电压和页脚偏置电压控制。

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