-
公开(公告)号：US11210757B2
公开(公告)日：2021-12-28
申请号：US16713472
申请日：2019-12-13
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Todd Martin , Tad Litwiller , Nishank Pathak , Mangesh P. Nijasure
IPC: G06T1/20 , H04L12/863 , H04L12/861
Abstract: A graphics processing unit (GPU) includes a packet management component that automatically aggregates data from input packets. In response to determining that a received first input packet does not indicate a send condition, and in response to determining that a generated output packet would be smaller than an output size threshold, the packet management component aggregates data corresponding to the first input packet with data corresponding to a second input packet stored at a packet buffer. In response to determining that a received third input packet indicates a send condition, the packet management component sends the aggregated data to a compute unit in an output packet and performs an operation indicated by the send condition.
-
公开(公告)号：US20210272354A1
公开(公告)日：2021-09-02
申请号：US17234692
申请日：2021-04-19
Applicant: Advanced Micro Devices, Inc.
Inventor： Mangesh P. Nijasure , Randy W. Ramsey , Todd Martin
Abstract: Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.
-
公开(公告)号：US11004258B2
公开(公告)日：2021-05-11
申请号：US16591287
申请日：2019-10-02
Applicant: Advanced Micro Devices, Inc.
Inventor： Mangesh P. Nijasure , Randy W. Ramsey , Todd Martin
Abstract: Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.
-
公开(公告)号：US10922868B2
公开(公告)日：2021-02-16
申请号：US16452831
申请日：2019-06-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Mangesh P. Nijasure , Todd Martin , Michael Mantor
Abstract: Improvements in the graphics processing pipeline that allow multiple pipelines to cooperate to render a single frame are disclosed. Two approaches are provided. In a first approach, world-space pipelines for the different graphics processing pipelines process all work for draw calls received from a central processing unit (CPU). In a second approach, the world-space pipelines divide up the work. Work that is divided is synchronized and redistributed at various points in the world-space pipeline. In either approach, the triangles output by the world-space pipelines are distributed to the screen-space pipelines based on the portions of the render surface overlapped by the triangles. Triangles are rendered by screen-space pipelines associated with the render surface portions overlapped by those triangles.
-
公开(公告)号：US10796483B2
公开(公告)日：2020-10-06
申请号：US16254304
申请日：2019-01-22
Applicant: Advanced Micro Devices, Inc.
Inventor： Saad Arrabi , Mangesh P. Nijasure , Todd Martin
Abstract: Techniques for removing reset indices from, and identifying primitives in, an index stream that defines a set of primitives to be rendered, are disclosed. The index stream may be specified by an application program executing on the central processing unit. The technique involves classifying the primitive topology for the index stream as either requiring an offset-based technique or requiring a non-offset-based technique. This classification is done by determining whether, according to the primitive topology, each subsequent index can form a primitive with prior indices (e.g., line strip, triangle strip). If each subsequent index can form a primitive with prior indices, then the technique used is the non-offset-based technique. If each subsequent index does not form a primitive with prior indices, but instead at least two indices are required to form a new primitive (e.g., line list, triangle list), then the technique used is the offset-based technique.
-
Patent Agency Ranking
公开(公告)号：US10600142B2
公开(公告)日：2020-03-24
申请号：US15832131
申请日：2017-12-05
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Usame Ceylan , Young In Yeo , Todd Martin , Vineet Goel
Abstract: A compute unit accesses a chunk of bits that represent indices of vertices of a graphics primitive. The compute unit sets values of a first bit to indicate whether the chunk is monotonic or ordinary, second bits to define an offset that is determined based on values of indices in the chunk, and sets of third bits that determine values of the indices in the chunk based on the offset defined by the second bits. The compute unit writes a compressed chunk represented by the first bit, the second bits, and the sets of third bits to a memory. The compressed chunk is decompressed and the decompressed indices are written to an index buffer. In some embodiments, the indices are decompressed based on metadata that includes offsets that are determined based on values of the indices and bitfields that indicate characteristics of the indices.
-
公开(公告)号：US20190228574A1
公开(公告)日：2019-07-25
申请号：US16254304
申请日：2019-01-22
Applicant: Advanced Micro Devices, Inc.
Inventor： Saad Arrabi , Mangesh P. Nijasure , Todd Martin
Abstract: Techniques for removing reset indices from, and identifying primitives in, an index stream that defines a set of primitives to be rendered, are disclosed. The index stream may be specified by an application program executing on the central processing unit. The technique involves classifying the primitive topology for the index stream as either requiring an offset-based technique or requiring a non-offset-based technique. This classification is done by determining whether, according to the primitive topology, each subsequent index can form a primitive with prior indices (e.g., line strip, triangle strip). If each subsequent index can form a primitive with prior indices, then the technique used is the non-offset-based technique. If each subsequent index does not form a primitive with prior indices, but instead at least two indices are required to form a new primitive (e.g., line list, triangle list), then the technique used is the offset-based technique.
-
公开(公告)号：US20180144536A1
公开(公告)日：2018-05-24
申请号：US15360395
申请日：2016-11-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Saad Arrabi , Mangesh P. Nijasure , Todd Martin
CPC classification number: G06T15/005 , G06T15/80 , G09G5/00
Abstract: Techniques for removing duplicate indices from an index stream are disclosed. The techniques involve dividing the indices into chunks. For any particular chunk, the techniques involve examining each index in the chunk to determine whether a “match” exists for that index within a reuse depth sliding window. The reuse depth sliding window includes a fixed number of indices immediately prior to the index being examined for a match. If a match exists, then the index is marked as non-unique and is assigned a position value equal to the position value of the matching index. If a match does not exist, then the index is marked as unique and assigned the next available position value for the chunk. After assigning position values to indices in a chunk, the indices in the chunk are transmitted to a vertex shader stage for processing in the order indicated by the position values.
-
公开(公告)号：US20180082470A1
公开(公告)日：2018-03-22
申请号：US15389481
申请日：2016-12-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Mangesh P. Nijasure , Randy W. Ramsey , Todd Martin
Abstract: Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.
-
公开(公告)号：US11527033B2
公开(公告)日：2022-12-13
申请号：US16825600
申请日：2020-03-20
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Saad Arrabi , Vishrut Vaibhav , Mangesh P. Nijasure , Todd Martin
IPC: G06T15/00
Abstract: A graphics pipeline includes a tessellator stage having a sub-patch distributor and a plurality of tessellators. The sub-patch distributor divides an input patch into a plurality of sub-primitive groups, with the primitive group limit governing the maximum permissible size for a given group of sub-primitives to be assigned to a tessellator. The sub-patch distributor recursively identifies a plurality of regions of the input patch, with the size and number of primitives of each region based on the specified primitive group limit. The sub-patch distributor assigns different regions to different sub-patch groups and distributes the sub-patch groups among the plurality of tessellators.
-
-
-
-
-
-
-
-
-
Search Results
35
records
(took 0.021 seconds)
