公开(公告)号：US20240070961A1

公开(公告)日：2024-02-29

申请号：US18089456

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael John Livesley ,  Vishrut Vaibhav ,  Tad Robert Litwiller

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06T2210/52

Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include in a coarse binning pass, generating a sorted set of draw calls, based on geometry processed through a world space pipeline and vertex indices obtained from an input assembler.

公开(公告)号：US20240087078A1

公开(公告)日：2024-03-14

申请号：US18337322

申请日：2023-06-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander Fuad Ashkar ,  Vishrut Vaibhav ,  Manu Rastogi ,  Harry J. Wise

IPC: G06T1/60 ,  G06T1/20 ,  G06T15/00 ,  G06T15/40

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T15/005 ,  G06T15/40

Abstract: Methods, devices, and systems for rendering primitives in a frame. During a visibility pass, state packets are processed to determine a register state, and the register state is stored in a memory device. During a rendering pass, the state packets are discarded and the register state is read from the memory device. In some implementations, a graphics pipeline is configured during the visibility pass based on the register state determined by processing the state packets, and the graphics pipeline is configured during the rendering pass based on the register state read from the memory device. In some implementations, replay control packets, draw packets, and the state packets, from a packet stream, are processed during the visibility pass; the draw packets are modified based on visibility information determined during the visibility pass; and the replay control packets and draw packets are processed, during the rendering pass.

公开(公告)号：US11527033B2

公开(公告)日：2022-12-13

申请号：US16825600

申请日：2020-03-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Saad Arrabi ,  Vishrut Vaibhav ,  Mangesh P. Nijasure ,  Todd Martin

IPC: G06T15/00

Abstract: A graphics pipeline includes a tessellator stage having a sub-patch distributor and a plurality of tessellators. The sub-patch distributor divides an input patch into a plurality of sub-primitive groups, with the primitive group limit governing the maximum permissible size for a given group of sub-primitives to be assigned to a tessellator. The sub-patch distributor recursively identifies a plurality of regions of the input patch, with the size and number of primitives of each region based on the specified primitive group limit. The sub-patch distributor assigns different regions to different sub-patch groups and distributes the sub-patch groups among the plurality of tessellators.

公开(公告)号：US20240412442A1

公开(公告)日：2024-12-12

申请号：US18208087

申请日：2023-06-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Vishrut Vaibhav ,  Mangesh Prabhakar Nijasure

IPC: G06T15/00 ,  G06T15/80

Abstract: An accelerated processing unit (APU) is configured to perform one or more attribute shading operations at a fragment shader. To this end, the APU includes a processor core configured to assemble one or more primitives from generated vertex shading data. The processor core culls one or more primitives to produce a set of surviving primitives and identifies which primitives of the set of surviving primitives are visible in a bin. The processor core then provides data identifying the visible primitives in the bin to a fragment shader. Based on the data identifying the visible primitives in the bin, the fragment shader generates attribute shading data for each visible primitive in the bin.

公开(公告)号：US20240169641A1

公开(公告)日：2024-05-23

申请号：US18193988

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Vishrut Vaibhav ,  Michael John Livesley ,  Tad Robert Litwiller

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06T2210/52

Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include providing indices and vertices to a culling shader; culling primitives and outputting primitives and indices that are not culled; and generating information for a fine binning pass based on the indices and primitives that are not culled.