公开(公告)号：US20250007861A1

公开(公告)日：2025-01-02

申请号：US18345957

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Bryan P. Broussard ,  Chintan S. Patel ,  Eric Christopher Morton ,  Jeffrey Lynn Freeman ,  Vydhyanathan Kalyanasundharam

IPC: H04L49/25

Abstract: The disclosed device includes memory channel interfaces and mesh lanes each corresponding to a particular memory channel interface. The device also includes ports and various routing elements interconnecting the ports, mesh lanes, memory channel interfaces. The device further includes a control circuit configured to receive a data packet on a port, select a mesh lane based on a destination of the data packet, and forward the data packet to the selected mesh lane via a routing element. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12174747B2

公开(公告)日：2024-12-24

申请号：US17556617

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Chintan S. Patel ,  Guhan Krishnan ,  Andrew William Lueck ,  Sreenath Thangarajan

IPC: G06F12/0897

Abstract: A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.

公开(公告)号：US12001265B2

公开(公告)日：2024-06-04

申请号：US17483694

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Christopher T. Weaver ,  Indrani Paul ,  Mihir Shaileshbhai Doctor ,  John P. Petry ,  Stephen V. Kosonocky ,  Thomas J. Gibney ,  Jose G. Cruz ,  Pravesh Gupta ,  Chintan S. Patel

IPC: G06F1/00 ,  G06F1/3234 ,  G06F3/06 ,  G06F11/14

CPC classification number: G06F1/3275 ,  G06F1/3265 ,  G06F3/0625 ,  G06F3/0635 ,  G06F3/0673 ,  G06F11/1469 ,  G06F2201/84

Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.

公开(公告)号：US20220091991A1

公开(公告)日：2022-03-24

申请号：US17031834

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravindra N. Bhargava ,  Ganesh Balakrishnan ,  Joe Sargunaraj ,  Chintan S. Patel ,  Girish Balaiah Aswathaiya ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0891 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0831 ,  G06F9/46

Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.

公开(公告)号：US20200259747A1

公开(公告)日：2020-08-13

申请号：US16795459

申请日：2020-02-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Alan Dodson Smith ,  Chintan S. Patel ,  Eric Christopher Morton ,  Vydhyanathan Kalyanasundharam ,  Narendra Kamat

IPC: H04L12/803 ,  G06F13/36 ,  G06F9/50

Abstract: Systems, apparatuses, and methods for dynamic buffer management in multi-client token flow control routers are disclosed. A system includes at least one or more processing units, a memory, and a communication fabric with a plurality of routers coupled to the processing unit(s) and the memory. A router servicing multiple active clients allocates a first number of tokens to each active client. The first number of tokens is less than a second number of tokens needed to saturate the bandwidth of each client to the router. The router also allocates a third number of tokens to a free pool, with tokens from the free pool being dynamically allocated to different clients. The third number of tokens is equal to the difference between the second number of tokens and the first number of tokens. An advantage of this approach is reducing the amount of buffer space needed at the router.

公开(公告)号：US20190259448A1

公开(公告)日：2019-08-22

申请号：US15902580

申请日：2018-02-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Chintan S. Patel ,  Vamsi Krishna Alla ,  Alan Dodson Smith

IPC: G11C11/406 ,  G06F13/16

CPC classification number: G06F1/3275 ,  G06F1/3287

Abstract: Systems, apparatuses, and methods for using a scoreboard to track updates to configuration state registers are disclosed. A system includes one or more processing nodes, one or more memory devices, a plurality of configuration state registers, and a communication fabric coupled to the processing unit(s) and memory device(s). The system uses a scoreboard to track updates to the configuration state registers during run-time. Prior to a node going into a power-gated state, the system stores only those configuration state registers that have changed. This reduces the amount of data written to memory on each transition into power-gated state, and increases the amount of time the node can spend in the power-gated state. Also, configuration state registers are grouped together to match the memory access granularity, and each group of configuration state registers has a corresponding scoreboard entry.”

公开(公告)号：US20190132249A1

公开(公告)日：2019-05-02

申请号：US15796528

申请日：2017-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Alan Dodson Smith ,  Chintan S. Patel ,  Eric Christopher Morton ,  Vydhyanathan Kalyanasundharam ,  Narendra Kamat

IPC: H04L12/803

Abstract: Systems, apparatuses, and methods for dynamic buffer management in multi-client token flow control routers are disclosed. A system includes at least one or more processing units, a memory, and a communication fabric with a plurality of routers coupled to the processing unit(s) and the memory. A router servicing multiple active clients allocates a first number of tokens to each active client. The first number of tokens is less than a second number of tokens needed to saturate the bandwidth of each client to the router. The router also allocates a third number of tokens to a free pool, with tokens from the free pool being dynamically allocated to different clients. The third number of tokens is equal to the difference between the second number of tokens and the first number of tokens. An advantage of this approach is reducing the amount of buffer space needed at the router.

公开(公告)号：US20190129693A1

公开(公告)日：2019-05-02

申请号：US15796521

申请日：2017-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Alan Dodson Smith

IPC: G06F7/498 ,  G06F17/30

CPC classification number: G06F7/4988 ,  G06F7/535 ,  G06F16/9017 ,  G06F2207/5354

Abstract: Systems, apparatuses, and methods for implementing a fractional pointer lookup table are disclosed. A system includes a fractional pointer lookup table and control logic coupled to the table. The control logic performs an access to the table with a numerator and a denominator, wherein the numerator and the denominator are integers. The control logic receives a result of the lookup, wherein the result is either a rounded-up value of a quotient of the numerator and denominator or a rounded-down value of the quotient. In one embodiment, the control logic provides a fractional pointer to the table with each access and receives a fractional pointer limit from the table. The control logic initializes the fractional pointer to zero, increments the fractional pointer after each access to the table, and resets the fractional pointer to zero when the fractional pointer reaches the fractional pointer limit.

公开(公告)号：US20250004943A1

公开(公告)日：2025-01-02

申请号：US18345974

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Edgar Munoz ,  Chintan S. Patel ,  Gregg Donley ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0802

Abstract: The disclosed device includes a first register that stores a cumulative delta value and a second register that stores an average cache hit rate. The device also includes a control circuit that calculates a cache hit rate and updates the cumulative delta value based on the cache hit rate and the average cache hit rate. The control circuit also updates the average cache hit rate based on the updated cumulative delta value, and can update a cache allocation policy based on the updated average cache hit rate. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240427704A1

公开(公告)日：2024-12-26

申请号：US18824818

申请日：2024-09-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Alexander J. Branover ,  Benjamin Tsien ,  Edgar Munoz ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0871 ,  G06F12/0811 ,  G06F12/0864

Abstract: A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.