公开(公告)号：US11470004B2

公开(公告)日：2022-10-11

申请号：US17027914

申请日：2020-09-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Narendra Kamat

IPC: H04L47/127 ,  H04L43/067 ,  H04L43/0876 ,  H04L43/16 ,  H04L47/10 ,  H04L47/30

Abstract: Graded throttling for network-on-chip traffic, including: calculating, by an agent of a network-on-chip, a number of outstanding transactions issued by the agent; determining that the number of outstanding transactions meets a threshold; and implementing, by the agent, in response to the number of outstanding transactions meeting the threshold, a traffic throttling policy.

公开(公告)号：US12066960B2

公开(公告)日：2024-08-20

申请号：US17562457

申请日：2021-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Narendra Kamat

IPC: G06F13/28 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/10 ,  G06F12/1072 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F12/10 ,  G06F13/4027 ,  G06F2212/65

Abstract: Systems, devices, and methods for direct memory access. A system direct memory access (SDMA) device disposed on a processor die sends a message which includes physical addresses of a source buffer and a destination buffer, and a size of a data transfer, to a data fabric device. The data fabric device sends an instruction which includes the physical addresses of the source and destination buffer, and the size of the data transfer, to first agent devices. Each of the first agent devices reads a portion of the source buffer from a memory device at the physical address of the source buffer. Each of the first agent devices sends the portion of the source buffer to one of second agent devices. Each of the second agent devices writes the portion of the source buffer to the destination buffer.

公开(公告)号：US20200259747A1

公开(公告)日：2020-08-13

申请号：US16795459

申请日：2020-02-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Alan Dodson Smith ,  Chintan S. Patel ,  Eric Christopher Morton ,  Vydhyanathan Kalyanasundharam ,  Narendra Kamat

IPC: H04L12/803 ,  G06F13/36 ,  G06F9/50

Abstract: Systems, apparatuses, and methods for dynamic buffer management in multi-client token flow control routers are disclosed. A system includes at least one or more processing units, a memory, and a communication fabric with a plurality of routers coupled to the processing unit(s) and the memory. A router servicing multiple active clients allocates a first number of tokens to each active client. The first number of tokens is less than a second number of tokens needed to saturate the bandwidth of each client to the router. The router also allocates a third number of tokens to a free pool, with tokens from the free pool being dynamically allocated to different clients. The third number of tokens is equal to the difference between the second number of tokens and the first number of tokens. An advantage of this approach is reducing the amount of buffer space needed at the router.

公开(公告)号：US20190132249A1

公开(公告)日：2019-05-02

申请号：US15796528

申请日：2017-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Alan Dodson Smith ,  Chintan S. Patel ,  Eric Christopher Morton ,  Vydhyanathan Kalyanasundharam ,  Narendra Kamat

IPC: H04L12/803

Abstract: Systems, apparatuses, and methods for dynamic buffer management in multi-client token flow control routers are disclosed. A system includes at least one or more processing units, a memory, and a communication fabric with a plurality of routers coupled to the processing unit(s) and the memory. A router servicing multiple active clients allocates a first number of tokens to each active client. The first number of tokens is less than a second number of tokens needed to saturate the bandwidth of each client to the router. The router also allocates a third number of tokens to a free pool, with tokens from the free pool being dynamically allocated to different clients. The third number of tokens is equal to the difference between the second number of tokens and the first number of tokens. An advantage of this approach is reducing the amount of buffer space needed at the router.

公开(公告)号：US12113712B2

公开(公告)日：2024-10-08

申请号：US17032054

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Narendra Kamat ,  Vydhyanathan Kalyanasundharam ,  Gregg Donley ,  Ashwin Chincholi

IPC: H04L47/20 ,  G06F15/78 ,  H04L47/24 ,  H04L49/109

CPC classification number: H04L47/20 ,  G06F15/7825 ,  H04L47/24 ,  H04L49/109

Abstract: Dynamic network-on-chip traffic throttling, including: determining, by a detector module of a network-on-chip, that a predefined condition is met; sending, by the detector module, a signal to a mediator module of the network-on-chip; and sending, in response to the signal, by the mediator module, an indication to a plurality of agents to implement a traffic throttling policy.

公开(公告)号：US20240111442A1

公开(公告)日：2024-04-04

申请号：US17936809

申请日：2022-09-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Shang Yang ,  Jun Lei ,  Gia Tung Phan ,  Oswin Hall ,  Benjamin Tsien ,  Narendra Kamat

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679

Abstract: Systems, apparatuses, and methods for prefetching data by a display controller. From time to time, a performance-state change of a memory are performed. During such changes, a memory clock frequency is changed for a memory subsystem storing frame buffer(s) used to drive pixels to a display device. During the performance-state change, memory accesses may be temporarily blocked. To sustain a desired quality of service for the display, a display controller is configured to prefetch data in advance of the performance-state change. In order to ensure the display controller has sufficient memory bandwidth to accomplish the prefetch, bandwidth reduction circuitry in clients of the system are configured to temporarily reduce memory bandwidth of corresponding clients.

公开(公告)号：US10608943B2

公开(公告)日：2020-03-31

申请号：US15796528

申请日：2017-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Alan Dodson Smith ,  Chintan S. Patel ,  Eric Christopher Morton ,  Vydhyanathan Kalyanasundharam ,  Narendra Kamat

IPC: G01R31/08 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26 ,  H04L12/803 ,  G06F9/50 ,  G06F13/36 ,  H04L12/863

Abstract: Systems, apparatuses, and methods for dynamic buffer management in multi-client token flow control routers are disclosed. A system includes at least one or more processing units, a memory, and a communication fabric with a plurality of routers coupled to the processing unit(s) and the memory. A router servicing multiple active clients allocates a first number of tokens to each active client. The first number of tokens is less than a second number of tokens needed to saturate the bandwidth of each client to the router. The router also allocates a third number of tokens to a free pool, with tokens from the free pool being dynamically allocated to different clients. The third number of tokens is equal to the difference between the second number of tokens and the first number of tokens. An advantage of this approach is reducing the amount of buffer space needed at the router.

公开(公告)号：US11876718B2

公开(公告)日：2024-01-16

申请号：US17961508

申请日：2022-10-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Narendra Kamat

IPC: H04L47/127 ,  H04L43/067 ,  H04L43/0876 ,  H04L43/16 ,  H04L47/10 ,  H04L47/30

CPC classification number: H04L47/127 ,  H04L43/067 ,  H04L43/0876 ,  H04L43/16 ,  H04L47/29 ,  H04L47/30

Abstract: Graded throttling for network-on-chip traffic, including: calculating, by an agent of a network-on-chip, a number of outstanding transactions issued by the agent; determining that the number of outstanding transactions meets a threshold; and implementing, by the agent, in response to the number of outstanding transactions meeting the threshold, a traffic throttling policy.

公开(公告)号：US20220197840A1

公开(公告)日：2022-06-23

申请号：US17562457

申请日：2021-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Narendra Kamat

IPC: G06F13/28 ,  G06F12/10 ,  G06F13/40

Abstract: Systems, devices, and methods for direct memory access. A system direct memory access (SDMA) device disposed on a processor die sends a message which includes physical addresses of a source buffer and a destination buffer, and a size of a data transfer, to a data fabric device. The data fabric device sends an instruction which includes the physical addresses of the source and destination buffer, and the size of the data transfer, to first agent devices. Each of the first agent devices reads a portion of the source buffer from a memory device at the physical address of the source buffer. Each of the first agent devices sends the portion of the source buffer to one of second agent devices. Each of the second agent devices writes the portion of the source buffer to the destination buffer.

公开(公告)号：US11210248B2

公开(公告)日：2021-12-28

申请号：US16723709

申请日：2019-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Narendra Kamat

IPC: G06F13/28 ,  G06F12/10 ,  G06F13/40

Abstract: Systems, devices, and methods for direct memory access. A system direct memory access (SDMA) device disposed on a processor die sends a message which includes physical addresses of a source buffer and a destination buffer, and a size of a data transfer, to a data fabric device. The data fabric device sends an instruction which includes the physical addresses of the source and destination buffer, and the size of the data transfer, to first agent devices. Each of the first agent devices reads a portion of the source buffer from a memory device at the physical address of the source buffer. Each of the first agent devices sends the portion of the source buffer to one of second agent devices. Each of the second agent devices writes the portion of the source buffer to the destination buffer.