公开(公告)号：US10916429B2

公开(公告)日：2021-02-09

申请号：US16705018

申请日：2019-12-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard Hunt ,  William T. Chen ,  Chih-Pin Hung ,  Chen-Chao Wang

IPC: H01L21/00 ,  H01L21/108 ,  H01L23/16 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/768 ,  H01L23/04 ,  H01L23/48 ,  H01L23/485 ,  H01L23/528 ,  H01L25/065 ,  H01L27/108 ,  H01L23/31

Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.

公开(公告)号：US10903561B2

公开(公告)日：2021-01-26

申请号：US16388828

申请日：2019-04-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Sheng-Chi Hsieh ,  Chen-Chao Wang ,  Teck-Chong Lee

IPC: H01Q1/38 ,  H01Q23/00 ,  H01L23/00 ,  H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L23/13 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/15

Abstract: A semiconductor device package includes a first glass carrier, a package body, a first circuit layer and a first antenna layer. The first circuit layer is disposed on the first surface of the first glass carrier. The first circuit layer has a redistribution layer (RDL). The package body is disposed on the first circuit layer. The package body has an interconnection structure penetrating the package body and is electrically connected to the RDL of the first circuit layer. The first antenna layer is disposed on the second surface of the first glass carrier.

公开(公告)号：US10535521B2

公开(公告)日：2020-01-14

申请号：US16297480

申请日：2019-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard Hunt ,  William T. Chen ,  Chih-Pin Hung ,  Chen-Chao Wang

IPC: H01L21/00 ,  H01L21/108 ,  H01L23/16 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/768 ,  H01L23/04 ,  H01L23/48 ,  H01L23/485 ,  H01L23/528 ,  H01L25/065 ,  H01L27/108 ,  H01L23/31

Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the second portion of the first trace is disposed between and spaced from opposing sidewalls of the dielectric layer defining the first opening.

公开(公告)号：US09728451B2

公开(公告)日：2017-08-08

申请号：US14465699

申请日：2014-08-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Ying-Te Ou

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L21/302 ,  H01L21/48 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L21/76877 ,  H01L21/302 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49513 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/04026 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83365 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10158 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.

公开(公告)号：US20140363967A1

公开(公告)日：2014-12-11

申请号：US14465699

申请日：2014-08-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Ying-Te Ou

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/302

CPC classification number: H01L21/76877 ,  H01L21/302 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49513 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/04026 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83365 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10158 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.