公开(公告)号：US11637172B2

公开(公告)日：2023-04-25

申请号：US17083281

申请日：2020-10-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Teck-Chong Lee

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01L23/14 ,  H01L23/15 ,  H01L23/00

Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

公开(公告)号：US10475718B2

公开(公告)日：2019-11-12

申请号：US15599379

申请日：2017-05-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Hung-Yi Lin ,  Cheng-Yuan Kung ,  Teck-Chong Lee ,  Shiuan-Yu Lin

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/532 ,  H01L21/683 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16

Abstract: A semiconductor device package includes a dielectric layer, a first RDL, a second RDL, an inductor, a first electronic component and a second electronic component. The first RDL is adjacent to a first surface of the dielectric layer, and the first RDL includes first conductive pieces. The second RDL is adjacent to a second surface of the dielectric layer, and the second RDL includes second conductive pieces. The inductor is disposed in the dielectric layer. The inductor includes induction pillars, wherein each of the induction pillars is disposed through the dielectric layer, and each of the induction pillars is interconnected between a respective one of the first conductive pieces of the first RDL and a respective one of the second conductive pieces of the second RDL. The first electronic component and the second electronic component are between the first RDL and the second RDL, and electrically connected to each other through the inductor.

公开(公告)号：US12176259B2

公开(公告)日：2024-12-24

申请号：US17542187

申请日：2021-12-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Teck-Chong Lee

IPC: H01L23/31

Abstract: A semiconductor package structure includes a circuit pattern structure, an encapsulant and an anchoring structure. The encapsulant is disposed on the circuit pattern structure. The anchoring structure is disposed adjacent to an interface between the encapsulant and the circuit pattern structure, and is configured to reduce a difference between a variation of expansion of the encapsulant and a variation of expansion of the circuit pattern structure in an environment of temperature variation.

公开(公告)号：US12166009B2

公开(公告)日：2024-12-10

申请号：US18239722

申请日：2023-08-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan Chen ,  Meng-Kai Shih ,  Teck-Chong Lee ,  Shin-Luh Tarng ,  Chih-Pin Hung

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/528

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US11742324B2

公开(公告)日：2023-08-29

申请号：US17322764

申请日：2021-05-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan Chen ,  Meng-Kai Shih ,  Teck-Chong Lee ,  Shin-Luh Tarng ,  Chih-Pin Hung

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L21/566 ,  H01L23/5283 ,  H01L24/17 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/73253 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US11621220B2

公开(公告)日：2023-04-04

申请号：US17213006

申请日：2021-03-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Chih-Pin Hung ,  Teck-Chong Lee ,  Chih-Yi Huang

IPC: H01L23/02 ,  H01L23/498 ,  H01L23/00 ,  H01L23/544 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31

Abstract: An assembly structure and a method for manufacturing an assembly structure are provided. The assembly structure includes a wiring structure and a semiconductor element. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the at least one dielectric layer, and defines an accommodating recess recessed from a top surface of the wiring structure. The wiring structure has a smooth surface extending from the top surface of the wiring structure to a surface of the accommodating recess. The semiconductor element is disposed in the accommodating recess.

公开(公告)号：US11605877B2

公开(公告)日：2023-03-14

申请号：US16544415

申请日：2019-08-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Chi Hsieh ,  Chen-Chao Wang ,  Teck-Chong Lee ,  Chien-Hua Chen

IPC: H01Q1/22 ,  H01L23/498 ,  H01L23/00 ,  H01L23/66 ,  H01L23/31 ,  H01L23/552 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538 ,  H01Q9/16 ,  H01L23/15

Abstract: A semiconductor device package includes a glass carrier, a package body, a first circuit layer and a first antenna layer. The glass carrier has a first surface and a second surface opposite to the first surface. The package body is disposed on the first surface of the glass carrier. The package body has an interconnection structure penetrating the package body. The first circuit layer is disposed on the package body. The first circuit layer has a redistribution layer (RDL) electrically connected to the interconnection structure of the package body. The first antenna layer is disposed on the second surface of the glass carrier.

公开(公告)号：US11133423B2

公开(公告)日：2021-09-28

申请号：US16503318

申请日：2019-07-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Pin Tsai ,  Tsung-Yueh Tsai ,  Teck-Chong Lee

IPC: H01L31/02 ,  H01L25/16 ,  H01L31/0203

Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.

公开(公告)号：US11011496B2

公开(公告)日：2021-05-18

申请号：US16563716

申请日：2019-09-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan Chen ,  Meng-Kai Shih ,  Teck-Chong Lee ,  Shin-Luh Tarng ,  Chih-Pin Hung

IPC: H01L21/56 ,  H01L23/528 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US10903561B2

公开(公告)日：2021-01-26

申请号：US16388828

申请日：2019-04-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Sheng-Chi Hsieh ,  Chen-Chao Wang ,  Teck-Chong Lee

IPC: H01Q1/38 ,  H01Q23/00 ,  H01L23/00 ,  H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L23/13 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/15

Abstract: A semiconductor device package includes a first glass carrier, a package body, a first circuit layer and a first antenna layer. The first circuit layer is disposed on the first surface of the first glass carrier. The first circuit layer has a redistribution layer (RDL). The package body is disposed on the first circuit layer. The package body has an interconnection structure penetrating the package body and is electrically connected to the RDL of the first circuit layer. The first antenna layer is disposed on the second surface of the first glass carrier.