公开(公告)号：US09768103B2

公开(公告)日：2017-09-19

申请号：US14990425

申请日：2016-01-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Hui Wang ,  Ying-Te Ou

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H05K1/18 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/185 ,  H05K1/188 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49204 ,  Y10T29/49213

Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

公开(公告)号：US08841751B2

公开(公告)日：2014-09-23

申请号：US13748068

申请日：2013-01-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Ying-Te Ou

IPC: H01L29/06 ,  H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76877 ,  H01L21/302 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49513 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/04026 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83365 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10158 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.

Abstract translation: 本发明提供半导体晶片，半导体芯片和半导体封装。 半导体晶片包括第一焊盘，第一层间电介质和第二焊盘。 第一焊盘设置在半导体衬底的顶表面上，并且具有实心部分和多个通孔。 第一层间电介质覆盖第一焊盘。 第二焊盘设置在第一层间电介质上，具有实心部分和多个通孔，其中第一焊盘的通孔对应于第二焊盘的实心部分。

公开(公告)号：US10600759B2

公开(公告)日：2020-03-24

申请号：US15404093

申请日：2017-01-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin Hung ,  Ying-Te Ou ,  Pao-Nan Lee

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00 ,  H01L23/31

Abstract: In one or more embodiments, a semiconductor device includes a substrate, a first dielectric layer and a first conductive layer. The substrate includes a first surface and a second surface opposite the first surface. The first dielectric layer is on the first surface of the substrate. The first conductive layer is on the first surface of the substrate and includes a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer. The second portion of the first conductive layer extends from the first portion of the first conductive layer through the first dielectric layer to contact the first surface of the substrate.

公开(公告)号：US09711473B1

公开(公告)日：2017-07-18

申请号：US15054502

申请日：2016-02-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Cheng Kuo ,  Ying-Te Ou ,  Lu-Ming Lai

IPC: H01L23/28 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L24/13 ,  H01L21/561 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/10156 ,  H01L2924/00014

Abstract: A semiconductor die includes a semiconductor body, an insulating layer, a conductive circuit layer and at least one conductive bump. The semiconductor body has a first surface, a second surface and a side surface extending between the first surface and the second surface. The insulating layer is disposed on the first surface and the side surface of the semiconductor body. The insulating layer includes a first insulating layer over the semiconductor body and a second insulating layer over the first insulating later. The insulating layer includes a step structure. The conductive circuit layer is electrically connected to the first surface of the semiconductor body, the conductive circuit layer includes at least one pad, and the conductive bump is electrically connected to the pad.

公开(公告)号：US20140203412A1

公开(公告)日：2014-07-24

申请号：US13748068

申请日：2013-01-23

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chen-Chao Wang ,  Ying-Te Ou

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/302 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49513 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/04026 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83365 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10158 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.

Abstract translation: 本发明提供半导体晶片，半导体芯片和半导体封装。 半导体晶片包括第一焊盘，第一层间电介质和第二焊盘。 第一焊盘设置在半导体衬底的顶表面上，并且具有实心部分和多个通孔。 第一层间电介质覆盖第一焊盘。 第二焊盘设置在第一层间电介质上，具有实心部分和多个通孔，其中第一焊盘的通孔对应于第二焊盘的实心部分。

公开(公告)号：US08937387B2

公开(公告)日：2015-01-20

申请号：US13671409

申请日：2012-11-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Che-Hau Huang ,  Ying-Te Ou

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05681 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/83385 ,  H01L2224/85005 ,  H01L2224/85205 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: The disclosure concerns a semiconductor device having conductive vias. In an embodiment, the semiconductor device includes a substrate having at least one conductive via formed therein. The conductive via has a first end substantially coplanar with an inactive surface of the substrate. A circuit layer is disposed adjacent to an active surface of the substrate and electrically connected to a second end of the conductive via. A redistribution layer is disposed adjacent to the inactive surface of the substrate, the redistribution layer having a first portion disposed on the first end an electrically connected thereto, and a second portion positioned upward and away from the first portion. A die is disposed adjacent to the inactive surface of the substrate and electrically connected to the second portion of the redistribution layer.

Abstract translation: 本公开涉及具有导电通孔的半导体器件。 在一个实施例中，半导体器件包括其中形成有至少一个导电通孔的衬底。 导电通孔具有与基板的非活性表面基本上共面的第一端。 电路层设置成与衬底的有源表面相邻并且电连接到导电通孔的第二端。 再分配层邻近基板的非活性表面设置，再分配层具有设置在第一端上的电连接到其上的第一部分和位于上方并远离第一部分的第二部分。 模具靠近基板的非活性表面设置并电连接到再分布层的第二部分。

公开(公告)号：US11806710B2

公开(公告)日：2023-11-07

申请号：US16893150

申请日：2020-06-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsiao-Yen Lee ,  Ying-Te Ou ,  Chin-Cheng Kuo ,  Chung Hao Chen

IPC: B01L3/00 ,  H01L23/538 ,  H01L21/02

CPC classification number: B01L3/502738 ,  H01L21/02 ,  H01L23/5386

Abstract: A semiconductor package structure includes a substrate, a die and a conductive structure. The die is disposed on or within the substrate. The die has a first surface facing away from the substrate and includes a sensing region and a pad at the first surface of the die. The first surface of the die has a first edge and a second edge opposite to the first edge. The sensing region is disposed adjacent to the first edge. The pad is disposed away from the first edge. The conductive structure electrically connects the pad and the substrate. The sensing region has a first end distal to the first edge of the first surface of the die. A distance from the first end of the sensing region to a center of the pad is equal to or greater than a distance from the first end of the sensing region to the first edge of the first surface of the die.

公开(公告)号：US10236208B2

公开(公告)日：2019-03-19

申请号：US15184828

申请日：2016-06-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Cheng Kuo ,  Pao-Nan Lee ,  Chih-Pin Hung ,  Ying-Te Ou

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body.

公开(公告)号：US09728451B2

公开(公告)日：2017-08-08

申请号：US14465699

申请日：2014-08-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Ying-Te Ou

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L21/302 ,  H01L21/48 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L21/76877 ,  H01L21/302 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49513 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/04026 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83365 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10158 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.

公开(公告)号：US20140363967A1

公开(公告)日：2014-12-11

申请号：US14465699

申请日：2014-08-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Ying-Te Ou

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/302

CPC classification number: H01L21/76877 ,  H01L21/302 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49513 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/04026 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83365 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10158 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.