公开(公告)号：US11605877B2

公开(公告)日：2023-03-14

申请号：US16544415

申请日：2019-08-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Chi Hsieh ,  Chen-Chao Wang ,  Teck-Chong Lee ,  Chien-Hua Chen

IPC: H01Q1/22 ,  H01L23/498 ,  H01L23/00 ,  H01L23/66 ,  H01L23/31 ,  H01L23/552 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538 ,  H01Q9/16 ,  H01L23/15

Abstract: A semiconductor device package includes a glass carrier, a package body, a first circuit layer and a first antenna layer. The glass carrier has a first surface and a second surface opposite to the first surface. The package body is disposed on the first surface of the glass carrier. The package body has an interconnection structure penetrating the package body. The first circuit layer is disposed on the package body. The first circuit layer has a redistribution layer (RDL) electrically connected to the interconnection structure of the package body. The first antenna layer is disposed on the second surface of the glass carrier.

公开(公告)号：US10903561B2

公开(公告)日：2021-01-26

申请号：US16388828

申请日：2019-04-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Sheng-Chi Hsieh ,  Chen-Chao Wang ,  Teck-Chong Lee

IPC: H01Q1/38 ,  H01Q23/00 ,  H01L23/00 ,  H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L23/13 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/15

Abstract: A semiconductor device package includes a first glass carrier, a package body, a first circuit layer and a first antenna layer. The first circuit layer is disposed on the first surface of the first glass carrier. The first circuit layer has a redistribution layer (RDL). The package body is disposed on the first circuit layer. The package body has an interconnection structure penetrating the package body and is electrically connected to the RDL of the first circuit layer. The first antenna layer is disposed on the second surface of the first glass carrier.

公开(公告)号：US10472228B2

公开(公告)日：2019-11-12

申请号：US15680056

申请日：2017-08-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Cheng-Yuan Kung ,  Che-Hau Huang ,  Chin-Cheng Kuo

IPC: B81B7/00 ,  B81C1/00 ,  H03H9/64 ,  H03H9/54 ,  H03H9/05

Abstract: A Micro Electro-Mechanical System (MEMS) device package includes a first circuit layer, a partition wall, a MEMS component, a second circuit layer and a polymeric dielectric layer. The partition wall is disposed over the first circuit layer. The MEMS component is disposed over the partition wall and electrically connected to the first circuit layer. The first circuit layer, the partition wall and the MEMS component enclose a space. The second circuit layer is disposed over and electrically connected to the first circuit layer. The polymeric dielectric layer is disposed between the first circuit layer and the second circuit layer.

公开(公告)号：US11201125B2

公开(公告)日：2021-12-14

申请号：US15442492

申请日：2017-02-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Chi Hsieh ,  Hung-Yi Lin ,  Cheng-Yuan Kung ,  Pao-Nan Lee ,  Chien-Hua Chen

IPC: H01L23/66 ,  H01L23/498 ,  H03H3/08 ,  H03H9/05 ,  H03H9/10 ,  H03H3/02 ,  H01L23/64

Abstract: The present disclosure relates to a semiconductor package and a method of manufacturing the same. In some embodiments, a semiconductor package includes a substrate, at least one die, a sealing ring and an inductor. The at least one die is mounted on the substrate and includes a plurality of component structures operating with acoustic waves. The component structures are arranged on a side of the at least one die that faces the substrate. The sealing ring is disposed between the at least one die and the substrate and surrounds the component structures. The inductor is disposed in the substrate.

公开(公告)号：US11037846B2

公开(公告)日：2021-06-15

申请号：US16578088

申请日：2019-09-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Hsu-Chiang Shih ,  Cheng-Yuan Kung ,  Hung-Yi Lin

IPC: H01L21/56 ,  H01L23/28 ,  H01L23/66 ,  H01Q1/22

Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.

公开(公告)号：US10861840B2

公开(公告)日：2020-12-08

申请号：US15691014

申请日：2017-08-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Teck-Chong Lee ,  Chien-Hua Chen

IPC: H01L27/01 ,  H01L49/02 ,  H01L21/683

Abstract: An integrated passive component comprises a capacitor, a first passivation layer, an inductor, an insulation layer and an external contact. The first passivation layer surrounds the capacitor. The inductor is on the first passivation layer and electrically connected to the capacitor. The inductor comprises a plurality of conductive pillars. The insulation layer is on the first passivation layer and surrounds each of the conductive pillars. The insulation layer comprises a first surface adjacent to the first passivation layer, a second surface opposite to the first surface, and a side surface extending between the first surface and the second surface. A ratio of a width of each of the conductive pillars to a height of each of the conductive pillars is about 1:7. The external contact is electrically connected to the inductor and contacts the second surface of the insulation layer and the side surface of the insulation layer.

公开(公告)号：US10475734B2

公开(公告)日：2019-11-12

申请号：US16277962

申请日：2019-02-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua Chen ,  Sheng-Chi Hsieh ,  Cheng-Yuan Kung

IPC: H01L21/44 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H05K1/16

Abstract: A semiconductor device package includes: (1) a substrate having a first surface and a second surface opposite to the first surface; (2) a first patterned conductive layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first patterned conductive layer is adjacent to the substrate and opposite to the first surface of the first patterned conductive layer; (3) a first insulation layer on the first surface of the substrate and having a first surface and a second surface, wherein the second surface of the first insulation layer is adjacent to the substrate and opposite to the first surface of the first insulation layer; and (4) a second patterned conductive layer extending from the first surface of the first insulation layer to the second surface of the substrate, the second patterned conductive layer electrically connected to the first patterned conductive layer.

公开(公告)号：US09929132B2

公开(公告)日：2018-03-27

申请号：US15406530

申请日：2017-01-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Teck-Chong Lee ,  Chien-Hua Chen ,  Yung-Shun Chang ,  Pao-Nan Lee

IPC: H01L27/08 ,  H01L27/01 ,  H01L49/02 ,  H01L23/528 ,  H01L21/70

CPC classification number: H01L27/016 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/707 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/528 ,  H01L28/10 ,  H01L28/60 ,  H01L2224/4813 ,  H05K1/0306 ,  H05K1/185 ,  H05K2201/0154

Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

公开(公告)号：US20170103946A1

公开(公告)日：2017-04-13

申请号：US15179683

申请日：2016-06-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Chien-Hua Chen ,  Teck-Chong Lee

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/5227 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81447 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A semiconductor device includes a substrate, at least one integrated passive device, a first redistribution layer, a second redistribution layer, and conductive vias. The at least one integrated passive device includes at least one capacitor disposed adjacent to a first surface of the substrate. The first redistribution layer is disposed adjacent to the first surface of the substrate. The second redistribution layer is disposed adjacent to a second surface of the substrate. The conductive vias extend through the substrate, and electrically connect the first redistribution layer and the second redistribution layer.

公开(公告)号：US09577027B2

公开(公告)日：2017-02-21

申请号：US14724522

申请日：2015-05-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Teck-Chong Lee ,  Chien-Hua Chen ,  Yung-Shun Chang ,  Pao-Nan Lee

IPC: H01L27/08 ,  H01L49/02 ,  H01L27/01 ,  H01L21/768 ,  H01L21/48 ,  H05K1/03 ,  H05K1/18 ,  H01L23/498

CPC classification number: H01L27/016 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/707 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/528 ,  H01L28/10 ,  H01L28/60 ,  H01L2224/4813 ,  H05K1/0306 ,  H05K1/185 ,  H05K2201/0154

Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

Abstract translation: 半导体器件包括衬底，种子层，第一图案化金属层，电介质层和第二金属层。 种子层设置在基板的表面上。 第一图案化金属层设置在种子层上并具有第一厚度。 第一图案化金属层包括第一部分和第二部分。 电介质层设置在第一图案化金属层的第一部分上。 第二金属层设置在电介质层上，具有第二厚度，其中第一厚度大于第二厚度。 第一图案化金属层的第一部分，电介质层和第二金属层形成电容器。 第一图案化金属层的第一部分是电容器的下电极，第一图案化金属层的第二部分是电感器。