公开(公告)号：US11055102B2

公开(公告)日：2021-07-06

申请号：US16991858

申请日：2020-08-12

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta

IPC: G06F9/38 ,  G06F12/0815 ,  G06F12/084

Abstract: In an embodiment, at least one CPU processor and at least one coprocessor are included in a system. The CPU processor may issue operations to the coprocessor to perform, including load/store operations. The CPU processor may generate the addresses that are accessed by the coprocessor load/store operations, as well as executing its own CPU load/store operations. The CPU processor may include a memory ordering table configured to track at least one memory region within which there are outstanding coprocessor load/store memory operations that have not yet completed. The CPU processor may delay CPU load/store operations until the outstanding coprocessor load/store operations are complete. In this fashion, the proper ordering of CPU load/store operations and coprocessor load/store operations may be maintained.

公开(公告)号：US20190196834A1

公开(公告)日：2019-06-27

申请号：US16292003

申请日：2019-03-04

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Brett S. Feero ,  David Williamson ,  Ian D. Kountanis ,  Shih-Chieh Wen

IPC: G06F9/38 ,  G06F1/3287 ,  G06F1/3234 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3806 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/30058 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/452

Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.

公开(公告)号：US10007616B1

公开(公告)日：2018-06-26

申请号：US15062448

申请日：2016-03-07

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  David J. Williamson ,  Jonathan J. Tyler ,  Mary D. Brown

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0831 ,  G06F12/128

CPC classification number: G06F12/0875 ,  G06F9/3802 ,  G06F9/3806 ,  G06F12/0862 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/502

Abstract: In an embodiment, an apparatus includes a cache memory and a control circuit. The control circuit may be configured to pre-fetch and store a first quantity of instruction data in response to a determination that a first pre-fetch operation request is received after a reset and prior to a first end condition. The first end condition may depend on an amount of unused storage in the cache memory. The control circuit may be further configured to pre-fetch and store a second quantity of instruction data in response to a determination that a second pre-fetch operation request is received after the first end condition. The second quantity may be less than the first quantity.