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公开(公告)号：US20220094369A1
公开(公告)日：2022-03-24
申请号：US17027028
申请日：2020-09-21
Applicant: Apple Inc.
Inventor： Dusan Stepanovic , Mansour Keramat
IPC: H03M3/00
Abstract: Systems, apparatuses, and methods for performing digital pre-distortion compensation of digital-to-analog converter non-linearity are described. A correction circuit receives a digital input word and couples a portion of the most significant bits (MSB's) of the digital input word to a correction lookup table (LUT). A correction value is retrieved from a correction LUT entry that matches the MSB's of the digital input word. Next, the correction value is added to the original digital input word in the digital domain. Then, the sum generated by adding the correction value to the original digital input word is optionally clipped if the sum exceeds the DAC core's input range. Next, the DAC core converts the sum into an analog value that is representative of the digital input word. The above approach helps to reduce non-linearities introduced by the DAC core in an energy-efficient manner by performing a correction in the digital domain.
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公开(公告)号：US11196436B1
公开(公告)日：2021-12-07
申请号：US17027064
申请日：2020-09-21
Applicant: Apple Inc.
Inventor： Dusan Stepanovic , KiYoung Nam , Mansour Keramat
IPC: H03M1/10
Abstract: Systems, apparatuses, and methods for performing hybrid non-linearity correction for a digital-to-analog converter (DAC) are described. A circuit includes two correction LUTs, an edge-trim DAC, and a DAC core. A lookup of a first correction LUT is performed using a portion of the most significant bits (MSBs) of a received digital input value. A first correction value, retrieved from the first correction LUT, is applied to the digital input value to generate a corrected value. The corrected value is provided to the DAC core and to a second correction LUT. A second correction value, retrieved from the second correction LUT, is compared to the first correction value. If the second correction value is different from the first correction value, the difference is provided to the edge-trim DAC to generate an analog correction which is applied to an analog output of the DAC core.
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公开(公告)号：US11114938B1
公开(公告)日：2021-09-07
申请号：US17006700
申请日：2020-08-28
Applicant: Apple Inc.
Inventor： Soheil Golara , Ali Mesgarani , Mansour Keramat , Seyedeh Sedigheh Hashemi
IPC: H02M3/07
Abstract: A power supply circuit included in a computer system is configured to generate a particular voltage level on a regulated power supply node using multiple charge pump circuits coupled together via a regulation device to provide regulation. A first charge pump circuit is configured to, using a voltage of an input power supply node, generate an intermediate voltage level, which is regulated by the regulation device. The second charge pump is configured to generate a voltage level on the regulated power supply node using a regulated version of intermediate voltage level. An impedance of the regulation device is adjusted using results of comparing the voltage level of the regulated power supply node to a reference voltage.
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公开(公告)号：US10951848B2
公开(公告)日：2021-03-16
申请号：US16272431
申请日：2019-02-11
Applicant: Apple Inc.
Inventor： Hyunsik Park , Ali Mesgarani , Mansour Keramat , Dusan Stepanovic , Ashirwad Bahukhandi
Abstract: An image sensing system is disclosed. The image sensing system includes an array of pixel circuits and a multiplexer configured to convey an output signal from a selected one of the pixel circuits. The output signal from the selected one of the plurality of pixel circuits is converted from analog to digital by a successive approximation register (SAR) analog-to-digital converter (ADC). A control circuit is provided to cause the SAR ADC power cycling with shaped power control signal. The SAR ADC comparator pre-amp with integrate-reset causes reduced power to the theoretical limit for imaging systems. The control circuit causes quantization process of selected ones of the pixel circuits to be repeated one or more times during the processing.
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公开(公告)号：US10863122B2
公开(公告)日：2020-12-08
申请号：US16272283
申请日：2019-02-11
Applicant: Apple Inc.
Inventor： Nick Chang , Mansour Keramat , Hyunsik Park , Brian Liebowitz , Ashirwad Bahukhandi
Abstract: A pixel circuit and method for operating the same is disclosed. The circuit includes a first driver circuit coupled to receive an analog pixel data, transfer signal and reset signal. The circuit further includes a source follower transistor having a source terminal coupled to a column node, and a gate terminal coupled to the first driver circuit. The circuit further includes a second driver circuit coupled to receive the transfer signal and the reset signal. The second driver circuit is capacitively coupled to the column node through a first capacitor.
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Patent Agency Ranking
公开(公告)号：US10819361B2
公开(公告)日：2020-10-27
申请号：US16745173
申请日：2020-01-16
Applicant: Apple Inc.
Inventor： Tao Wang , Mansour Keramat , Yi Chun A. Fu
IPC: H03M1/10 , H01L23/528 , H01L27/10
Abstract: Capacitor arrays and methods of operating a digital to analog converter are described. In an embodiment, a capacitor array includes a unit capacitor (Cu) structure characterized by a unit capacitance value, a plurality of different super-unit capacitor structures, and a plurality of different sub-unit capacitor structures, each different sub-unit capacitor structure having a different capacitance defined by a division of the unit capacitance value.
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公开(公告)号：US10574249B2
公开(公告)日：2020-02-25
申请号：US15969547
申请日：2018-05-02
Applicant: Apple Inc.
Inventor： Tao Wang , Mansour Keramat , Yi Chun A. Fu
IPC: H03M1/10 , H01L23/528 , H01L27/10
Abstract: Capacitor arrays and methods of operating a digital to analog converter are described. In an embodiment, a capacitor array includes a unit capacitor (Cu) structure characterized by a unit capacitance value, a plurality of different super-unit capacitor structures, and a plurality of different sub-unit capacitor structures, each different sub-unit capacitor structure having a different capacitance defined by a division of the unit capacitance value.
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28.发明申请公开(公告)号：US20190341925A1
公开(公告)日：2019-11-07
申请号：US15969547
申请日：2018-05-02
Applicant: Apple Inc.
Inventor： Tao Wang , Mansour Keramat , Yi Chun A. Fu
IPC: H03M1/10 , H01L27/10 , H01L23/528
Abstract: Capacitor arrays and methods of operating a digital to analog converter are described. In an embodiment, a capacitor array includes a unit capacitor (Cu) structure characterized by a unit capacitance value, a plurality of different super-unit capacitor structures, and a plurality of different sub-unit capacitor structures, each different sub-unit capacitor structure having a different capacitance defined by a division of the unit capacitance value.
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公开(公告)号：US20190244894A1
公开(公告)日：2019-08-08
申请号：US15890135
申请日：2018-02-06
Applicant: Apple Inc.
Inventor： Yi Chun A. Fu , Mansour Keramat , Vijay Srinivas
Abstract: Capacitor structures with pitch-matched capacitor unit cells are described. In an embodiment, the capacitor unit cells are formed by interdigitated finger electrodes. The finger electrodes may be pitch-matched in multiple metal layers within a capacitor unit cell, and the finger electrodes may be pitch-matched among an array of capacitor unit cells. Additionally, border unit cells may be pitch-matched with the capacitor unit cells.
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公开(公告)号：US09966907B1
公开(公告)日：2018-05-08
申请号：US15426111
申请日：2017-02-07
Applicant: Apple Inc.
Inventor： Vahid Majidzadeh Bafar , Ashkan Borna , Mansour Keramat
CPC classification number: H03F1/52 , H03F1/34 , H03F3/45475 , H03F2200/258 , H03F2200/411 , H03F2200/66
Abstract: A method and apparatus for high-speed clipping and recovery in an amplifier circuit is disclosed. In one embodiment, a circuit includes an amplifier configured to amplify an incoming signal. The amplifier includes inverting and non-inverting inputs, and is configured to provide a differential output. An output limiting circuit is coupled across the differential output, and is configured to limit an amplitude of an output signal provided on the differential output responsive to an input signal exceeding a first amplitude threshold. An input limiting circuit is coupled between the inverting input and the non-inverting input of the amplifier. Responsive to the input signal exceeding a second amplitude threshold (greater than the first), the input limiting circuit is configured to limit the amplitude of the output signal.
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