Transient Booster for Zero Static Loadline Switching Regulator

    公开(公告)号:US20200007036A1

    公开(公告)日:2020-01-02

    申请号:US16502752

    申请日:2019-07-03

    Applicant: Apple Inc.

    Abstract: A zero static loadline switching regulator can include a controller having an integrating outer control loop that receives a first feedback signal corresponding regulator load and a reference signal and generates an intermediate feedback signal therefrom. The control circuit can also include an inner control loop that receives the intermediate feedback signal and a second feedback signal corresponding to a load on the regulator and generates an error signal used to control switching devices of the regulator. The control circuit can also include a transient response circuit configured to boost the error signal, for a predetermined time period after and responsive to a load transient. The error signal may be boosted to an intermediate value between its saturation level and its full scale level. The intermediate value may be predetermined or may be determined responsive to the magnitude of the load transient.

    Self-Contained Slot and Slot Duration Configuration in NR Systems

    公开(公告)号:US20190306856A1

    公开(公告)日:2019-10-03

    申请号:US16357844

    申请日:2019-03-19

    Applicant: Apple Inc.

    Abstract: Apparatuses, systems, and methods to dynamically indicate preference for self-contained slots and slot duration by a user equipment device (UE) in communication with a base station (e.g., a gNB) using a 5G NR radio access technology. A UE may determine to send an indication to a gNB indicating a preference for self-contained slots and slot duration for downlink and/or uplink communications utilizing one or more of the physical downlink control channel (PDCCH), the physical downlink shared channel (PDSCH), and/or acknowledgement messaging (ACK/NACK) for downlink communications, and utilizing one or more of the physical uplink control channel (PUCCH), the PDCCH, and/or the physical uplink shared channel (PUSCH) for uplink communications. The configuration of self-contained slots and slot duration for uplink and/or downlink may be based on one or more of average packet size, average packet rate, traffic type and UE processing capabilities.

    Synchronization Sequence Design for Device-to-Device Communication

    公开(公告)号:US20190089570A1

    公开(公告)日:2019-03-21

    申请号:US16110377

    申请日:2018-08-23

    Applicant: Apple Inc.

    CPC classification number: H04L27/2692 H04L27/2613 H04W56/001 H04W56/002

    Abstract: This disclosure relates to techniques for supporting narrowband device-to-device wireless communication, including possible techniques for providing synchronization sequences. A first wireless device may transmit a preamble of a device-to-device wireless communication with a second wireless device. The preamble may include a first synchronization sequence. The first synchronization sequence may include multiple repetitions of a basis sequence, multiplied by a cover code. The basis sequence may span multiple orthogonal frequency division multiplexing symbols.

    Control channel for UE power saving

    公开(公告)号:US12150147B2

    公开(公告)日:2024-11-19

    申请号:US18450953

    申请日:2023-08-16

    Applicant: Apple Inc.

    Abstract: A downlink control information (DCI), such as a blanking DCI (bDCI) message may be transmitted by a base station (e.g., eNB) and received by a mobile device (e.g., UE). The bDCI may indicate that the eNB will not transmit a subsequent DCI to the UE for a duration of time. The UE may be in continuous reception mode or connected discontinuous reception (C-DRX) mode. The UE may therefore determine to enter a sleep state or take other action. The bDCI may specify an explicit blanking duration, or an index indicating a blanking duration from a lookup table, and/or the blanking duration (and/or a blanking duration offset value) may be determined in advance, e.g., semi-statically. When the UE is in C-DRX mode, the UE may be configured such that either the sleep/wake period of the C-DRX mode or the blanking period of the bDCI may take precedence over the other.

Patent Agency Ranking