公开(公告)号：US20040007561A1

公开(公告)日：2004-01-15

申请号：US10194566

申请日：2002-07-12

Applicant: Applied Materials, Inc.

Inventor： Padmapani Nallan ,  Guangxiang Jin ,  Ajay Kumar

IPC: C23F001/00 ,  B44C001/22 ,  C03C015/00 ,  C03C025/68

CPC classification number: H01L21/31122

Abstract: A method for etching a high K dielectric material comprises etching in a first plasma comprising a halogen containing gas (e.g., chlorine) and a reducing gas (e.g., carbon monoxide) and removing post-etch residue in a second plasma comprising a residue cleaning gas (e.g., oxygen or a mixture of oxygen and nitrogen).

Abstract translation: 蚀刻高K电介质材料的方法包括在包含含卤素气体（例如氯）和还原气体（例如一氧化碳）的第一等离子体中蚀刻，并且在包含残留物清洁气体的第二等离子体中除去蚀刻后残留物 （例如，氧气或氧气和氮气的混合物）。

公开(公告)号：US20030211748A1

公开(公告)日：2003-11-13

申请号：US10143397

申请日：2002-05-09

Applicant: Applied Materials, Inc.

Inventor： Guangxiang Jin ,  Padmapani Nallan ,  Ajay Kumar

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/31122

Abstract: A method of etching high dielectric constant materials using a halogen gas, a reducing gas and an etch rate control gas chemistry.

Abstract translation: 使用卤素气体，还原气体和蚀刻速率控制气体化学来蚀刻高介电常数材料的方法。

公开(公告)号：US20030176075A1

公开(公告)日：2003-09-18

申请号：US10093050

申请日：2002-03-06

Applicant: Applied Materials, Inc.

Inventor： Anisul Khan ,  Ajay Kumar ,  Padmapani Nallan

IPC: H01L021/4763

CPC classification number: H01L21/3065 ,  G02B6/136

Abstract: The present invention provides novel etching techniques for etching SinullGe, employing SF6/fluorocarbon etch chemistries at a low bias power. These plasma conditions are highly selective to organic photoresist. The techniques of the present invention are suitable for fabricating optically smooth SinullGe surfaces. A cavity was etched in a layer of a first SinullGe composition using SF6/C4F8 etch chemistry at low bias power. The cavity was then filled with a second SinullGe composition having a higher refractive index than the first SinullGe composition. A waveguide was subsequently fabricated by depositing a cladding layer on the second SinullGe composition that was formed in the cavity. In a further embodiment a cluster tool is employed for executing processing steps of the present invention inside the vacuum environment of the cluster tool. In an additional embodiment a manufacturing system is provided for fabricating waveguides of the present invention. The manufacturing system includes a controller that is adapted for interacting with a plurality of fabricating stations.

Abstract translation: 本发明提供了用于蚀刻Si-Ge的新颖蚀刻技术，其采用SF6 /氟碳蚀刻化学品，以低偏压功率。 这些等离子体条件对有机光致抗蚀剂具有高选择性。 本发明的技术适用于制造光学平滑的Si-Ge表面。 在低偏压功率下，使用SF6 / C4F8蚀刻化学法在第一Si-Ge组合物的层中蚀刻空腔。 然后用具有比第一Si-Ge组合物更高的折射率的第二Si-Ge组合物填充空腔。 随后通过在形成在空腔中的第二Si-Ge组合物上沉积包覆层来制造波导。 在另一个实施例中，采用集群工具来在集群工具的真空环境内执行本发明的处理步骤。 在另外的实施例中，提供制造系统用于制造本发明的波导。 该制造系统包括适于与多个制造站相互作用的控制器。

公开(公告)号：US20030170986A1

公开(公告)日：2003-09-11

申请号：US10092795

申请日：2002-03-06

Applicant: Applied Materials, Inc.

Inventor： Padmapani C. Nallan ,  Guangxiang Jin ,  Ajay Kumar

IPC: H01L021/44 ,  H01L021/302 ,  H01L021/461

CPC classification number: H01L21/31116 ,  H01L21/31122

Abstract: A method of etching high dielectric constant materials using halogen gas and reducing gas chemistry. An embodiment of the method is accomplished using a 20 to 300 sccm of chlorine and 2 to 200 sccm of carbon monoxide, regulated to a total chamber pressure of 2-100 mTorr to etch a hafnium oxide layer.

Abstract translation: 使用卤素气体蚀刻高介电常数材料并减少气体化学的方法。 该方法的一个实施方案是使用20至300sccm的氯和2至200sccm的一氧化碳来实现，调节至总室压力为2-100mTorr以蚀刻氧化铪层。

公开(公告)号：US20010051439A1

公开(公告)日：2001-12-13

申请号：US09864705

申请日：2001-05-23

Applicant: Applied Materials, Inc.

Inventor： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC: H01L021/302

CPC classification number: H01L21/67069 ,  H01L21/3065 ,  H01L21/76232 ,  H01L27/1087 ,  Y10S156/916

Abstract: This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.

公开(公告)号：US20010019897A1

公开(公告)日：2001-09-06

申请号：US09853847

申请日：2001-05-11

Applicant: Applied Materials, Inc.

Inventor： Ajay Kumar ,  Anisul Khan ,  Jeffrey D. Chinn ,  Dragan V. Podlesnik

IPC: H01L021/302 ,  C23F003/00 ,  H01L021/461 ,  C23F001/02

CPC classification number: H01L21/67069 ,  H01J37/321 ,  H01J37/32935 ,  H01L21/3065

Abstract: This invention is directed to a method for plasma etching difficult to etch materials at a high etch rate. The method is particularly useful in plasma etching silicon nitride layers more than five microns thick. The method includes a plasma formed by energy provided from two separate power sources and a gaseous mixture that includes only an etchant gas and a sputtering gas. The power levels from the separate power sources and the ratio between the flow rates of the etchant gas and a sputtering gas can be advantageously adjusted to obtain etch rates of silicon nitride greater than two microns per minute. Additionally, an embodiment of the method of the invention provides a two etch step process which combines a high etch rate process with a low etch rate process to achieve high throughput while minimizing the likelihood of damage to underlying layers. The first etch step of the two-step method provides a high etch rate of about two microns per minute to remove substantially all of a layer to be etched the. In the second step, a low etch rate process having an etch rate below about two microns per minute is used remove any residual material not removed by the first etch step.

Abstract translation: 本发明涉及一种用于等离子体蚀刻的方法，其难以以高蚀刻速率蚀刻材料。 该方法在等离子体蚀刻中超过5微米厚的氮化硅层特别有用。 该方法包括通过由两个单独的电源提供的能量形成的等离子体和仅包括蚀刻剂气体和溅射气体的气体混合物。 可以有利地调节来自分离的电源的功率水平以及蚀刻剂气体和溅射气体的流量之间的比率，以获得大于每分钟2微米的氮化硅的蚀刻速率。 另外，本发明的方法的一个实施例提供了两个蚀刻步骤方法，其将高蚀刻速率工艺与低蚀刻速率工艺组合以实现高通量，同时最小化对下层的损伤的可能性。 两步法的第一蚀刻步骤提供了大约每分钟2微米的高蚀刻速率，以便基本上去除所有待蚀刻的层。 在第二步骤中，使用蚀刻速率低于每分钟约2微米的低蚀刻速率工艺去除通过第一蚀刻步骤未被去除的任何残留材料。

公开(公告)号：US20040209468A1

公开(公告)日：2004-10-21

申请号：US10418995

申请日：2003-04-17

Applicant: Applied Materials Inc.

Inventor： Ajay Kumar ,  Padmapani C. Nallan

IPC: H01L021/3205 ,  H01L021/4763 ,  H01L021/461 ,  H01L021/302

CPC classification number: H01L21/02071 ,  H01L21/31122 ,  H01L21/32137

Abstract: A method for fabricating a gate structure of a field effect transistor is disclosed. The gate structure is fabricated by sequentially etching a material stack comprising a gate electrode layer formed on a gate dielectric layer. Prior to etching the gate dielectric layer, polymeric residues formed on the substrate when the gate electrode is etched are removed. The polymeric residue is removed by exposing the substrate to a plasma comprising one or more fluorocarbon containing gases and at least one inert gas. structure.

Abstract translation: 公开了一种用于制造场效应晶体管的栅极结构的方法。 通过依次蚀刻包括形成在栅极电介质层上的栅电极层的材料堆叠来制造栅极结构。 在蚀刻栅极电介质层之前，去除在蚀刻栅电极时在衬底上形成的聚合物残留物。 通过将衬底暴露于包含一种或多种含碳氟化合物气体和至少一种惰性气体的等离子体来除去聚合物残余物。 结构体。

公开(公告)号：US20040206724A1

公开(公告)日：2004-10-21

申请号：US10418994

申请日：2003-04-17

Applicant: Applied Materials, Inc.

Inventor： Padmapani C. Nallan ,  Ajay Kumar ,  Guangxiang Jin

IPC: C23F001/00 ,  B44C001/22 ,  C03C015/00 ,  C03C025/68

CPC classification number: H01L21/31116 ,  C23F4/00 ,  H01L21/32137

Abstract: A method of plasma etching a metal layer (e.g., titanium (Ti), tantalum (Ta), tungsten (W), and the like) or a metal-containing layer (e.g., tantalum silicon nitride (TaSiN), titanium nitride (TiN), tungsten nitride (WN), and the like) formed on a hafnium-based dielectric material is disclosed. The metal/metal-containing layer is etched using a gas mixture comprising a halogen-containing gas and a fluorine-containing gas. The fluorine within the gas mixture provides a high etch selectivity for the hafnium-based dielectric material.

Abstract translation: 金属层（例如钛（Ti），钽（Ta），钨（W）等）等等离子体蚀刻或金属含有层（例如，钽氮化硅（TaSiN），氮化钛 ），氮化钨（WN）等）形成在铪基电介质材料上。 使用包含含卤素气体和含氟气体的气体混合物来蚀刻含金属/含金属层。 气体混合物中的氟提供了对铪基电介质材料的高蚀刻选择性。

公开(公告)号：US20040173572A1

公开(公告)日：2004-09-09

申请号：US10805890

申请日：2004-03-22

Applicant: Applied Materials, Inc.

Inventor： Padmapani C. Nallan ,  Guangxiang Jin ,  Ajay Kumar

IPC: C23F001/00

CPC classification number: H01L21/31116 ,  H01L21/31122

Abstract: A method of etching high dielectric constant materials using halogen gas and reducing gas chemistry. An embodiment of the method is accomplished using a 20 to 300 sccm of chlorine and 2 to 200 sccm of carbon monoxide, regulated to a total chamber pressure of 2-100 mTorr to etch a hafnium oxide layer.

公开(公告)号：US20040137749A1

公开(公告)日：2004-07-15

申请号：US10342087

申请日：2003-01-13

Applicant: Applied Materials, Inc.

Inventor： Chentsau Ying ,  Xiaoyi Chen ,  Chun Yan ,  Ajay Kumar

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L43/12 ,  H01L21/32136

Abstract: A method for removing conductive residue from a layer on a semiconductor substrate by exposing the substrate to a gas comprising a fluorine containing gas and a hydrogen containing gas. In one embodiment, the gas is excited to form a plasma that removes the conductive residue during fabrication of a magneto-resistive random access memory (MRAM) device.

Abstract translation: 一种通过将衬底暴露于包含含氟气体和含氢气体的气体从半导体衬底上的层去除导电残留物的方法。 在一个实施例中，气体被激发以形成在制造磁阻随机存取存储器（MRAM）器件期间除去导电残留物的等离子体。